Abstract: A method for smart defect review is disclosed. The method includes pre-processing a design layout into a plurality of layout based pattern groups, dividing the design layout into a plurality of cells, overlapping the cells belong to the same layout based pattern groups, extracting a plurality of defect data of all defects on a wafer, constructing a plurality of layout based defect composite pattern groups, executing layout pattern match to obtain each individual layout based defect composite pattern group, performing some defect sample selection rules to each layout based defect composite pattern group, sorting the layout based defect composite pattern groups into different defect types, obtaining a defect image file by reviewing different sample number of defect image from each layout based defect composite pattern group, and generating a defect pattern library or a defect yield prediction by performing a defect yield diagnosis to the defect image file.

Abstract: A method for smart defect review is disclosed. The method includes pre-processing a design layout into a plurality of layout based pattern groups, dividing the design layout into a plurality of cells, overlapping the cells belong to the same layout based pattern groups, extracting a plurality of defect data of all defects on a wafer, constructing a plurality of layout based defect composite pattern groups, executing layout pattern match to obtain each individual layout based defect composite pattern group, performing some defect sample selection rules to each layout based defect composite pattern group, sorting the layout based defect composite pattern groups into different defect types, obtaining a defect image file by reviewing different sample number of defect image from each layout based defect composite pattern group, and generating a defect pattern library or a defect yield prediction by performing a defect yield diagnosis to the defect image file.

Abstract: Features of a mask, when close enough to one another, can cause unwanted phantom images to print on an integrated circuit. Advantageously, potential locations of phantom images can be automatically identified from a mask layout. This technique can include creating perimeters or rings around features in the mask layout (in one case, after proximity correction). An overlap of perimeters/rings can be assigned a particular weight such that areas of greater overlap have a higher weight and areas of less overlap have a lower weight. If the weight of an overlap area exceeds a trigger weight, then an evaluation point can be added to the mask layout, thereby identifying that layout location as a potential location of a phantom image. After simulation of the mask layout, that layout location can be analyzed to determine if a phantom image would print.

Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

Abstract: Features of a mask, when close enough to one another, can cause unwanted phantom images to print on an integrated circuit. Advantageously, potential locations of phantom images can be automatically identified from a mask layout. This technique can include creating perimeters or rings around features in the mask layout (in one case, after proximity correction). An overlap of perimeters/rings can be assigned a particular weight such that areas of greater overlap have a higher weight and areas of less overlap have a lower weight. If the weight of an overlap area exceeds a trigger weight, then an evaluation point can be added to the mask layout, thereby identifying that layout location as a potential location of a phantom image. After simulation of the mask layout, that layout location can be analyzed to determine if a phantom image would print.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node's siblings and/or parent, and possibly other surrounding geometries, change the layout of the node as specified by the first cell.

Abstract: One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node's siblings and/or parent, and possibly other surrounding geometries, change the layout of the node as specified by the first cell.

Abstract: A method for optimal track assignment in a grid-based channel router. Initially, interconnection information is extracted from a global routing result. Multiple pin nets derived from the interconnection information are decomposed into simpler mapped segments. A channel grid map is then built and marked with existing objects. Next, a vertical constraint graph specifying the relative positions of the mapped segments is constructed. A first track is computed. A track assignment loop is repeated until all requisite connections are realized. The track assignment loop includes the steps of breaking cycles and long paths and collecting a set of feasible links. One or more weighting functions are assigned to each such feasible link. A dynamic programming approach is used to select an optimal set of feasible links according to the weighting functions. In addition, an optimal set of feasible links corresponding to unpreferred layers is collected by applying dynamic programming.

Abstract: An electronic design automation tool embodiment of the present invention comprises a five step process. In a first step, for each pin-master of arbitrary shape in a cell-master a pin access direction is identified, a region in which placing a via will connect a pin to a metal layer, and cause no design rule violation to other pin-masters, is physical bounded on the surface of a chip. Such a region is defined to be a "via-region" of the pin-master. In a second step, at least one "via-spot" within each via-region is identified that violates no design rules if vias are placed at these points. In a third step, vias are placed on each cell instance according to their via-spots. In a fourth step, a "maze-routing" is done to connect the neighboring same net pins by metal-1. In a fifth step, the vias on the pins connected by the maze-router are removed, leaving only one via on a pin if the connection for a current net is not complete.