Abstract: A FeRAM array configured in a ROM format is provided. The FeRAM array includes a memory array that has a plurality of segmented BL/PL arrays, and each segmented BL/PL array defines an I/O. A plurality of charge transfer sense amplifiers is further provided. Each charge transfer sense amplifier is associated with each I/O, and each charge transfer sense amplifier includes a cross coupled latch that is connected between a memory cell access portion and a reference voltage generation portion of the charge transfer sense amplifier. The reference voltage generation portion further includes a reference bitline (Crb) coupled to a reference voltage (Vr), and the reference bitline (Crb) is coupled to a pair of dummy capacitance cells. Each of the dummy capacitance cells is preset before reading at an opposite relative polarity.