Patents by Inventor Chin-Hsien Lin

Chin-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250070905
    Abstract: An optical input/output tray for management of optical fibers installed in a switch assembly is disclosed. The switch assembly has a co-packaged optics module with an optical data signal input and a laser input, and a front panel. The optical input/output tray includes a housing insertable in the switch assembly. A first set of adapters are connectable to the co-packaged optics module. A second set of adapters is connectable to the front panel. WDM components convert a plurality of multi-wavelength signals from the first set of adapters to a single multiplexed signal coupled to the second set of adapters. The WDM components converts a single multiplexed signal from the second set of adapters to multi-wavelength signals coupled to the first set of adapters. A fiber management structure in the housing communicates optical signals between the first set of adapters, the WDM components, and the second set of adapters.
    Type: Application
    Filed: February 15, 2024
    Publication date: February 27, 2025
    Inventors: Chin-Lung SU, Chang-Sheng Lin, Hsiao-Hsien Weng, Zong-Syun HE
  • Publication number: 20230364160
    Abstract: The present disclosure provides a method for treating Parkinson's disease by using Parabacteroides goldsteinii. The Parabacteroides goldsteinii of the present disclosure achieves the effect of treating Parkinson's disease through various efficacy experiments.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 16, 2023
    Inventors: Chin-Hsien Lin, Hsin-Chih Lai, Chia-Chen Lu, Tzu-Lung Lin, Po-I Wu
  • Patent number: 7218006
    Abstract: A multi-chip stack package mainly includes a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate with an active surface facing upwards. The redistribution structure includes a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads. The first intermediate pads, the second intermediate pads, and the external pads are formed on the first active surface of the first chip, wherein the first intermediate pads and the second intermediate pads are electrically connected with each other. The second chip is disposed on the redistribution structure, and electrically connected to the first intermediate pads. The second intermediate pads are electrically connected to the substrate through a plurality of bonding wires, so that the second chip and the substrate are electrically conducted, and the connection length of the bonding wires is reduced.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: May 15, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung-Kun Kang, Chin-Hsien Lin
  • Publication number: 20060242967
    Abstract: A thermoelectric wafer chuck is disclosed. The thermoelectric wafer chuck includes a wafer support surface for supporting a wafer; and a thermoelectric module provided in thermal contact with the wafer support surface for heating and/or cooling the wafer support surface and wafer.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 2, 2006
    Inventors: Yu-Liang Lin, Chin-Hsien Lin, Jerry Hwang
  • Publication number: 20060091560
    Abstract: A multi-chip stack package mainly comprises a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate by an active surface facing upwards. The redistribution structure comprises a plurality of first intermediate pads, a plurality of second intermediate pads and a plurality of external pads. The first intermediate pads, the second intermediate pads, and the external pads are formed on the first active surface of the first chip, wherein the first intermediate pads and the second intermediate pads are electrically connected with each other. The second chip is disposed on the redistribution structure, and electrically connected to the first intermediate pads. The second intermediate pads are electrically connected to the substrate through a plurality of bonding wires, so that the second chip and the substrate are electrically conducted, and the connection length of the bonding wires is reduced.
    Type: Application
    Filed: October 26, 2005
    Publication date: May 4, 2006
    Inventors: Jung-Kun Kang, Chin-Hsien Lin
  • Patent number: 7037750
    Abstract: A method of manufacturing a package is disclosed. The manufacturing method includes the steps of providing a substrate having an opening, disposing a metal slice on a bottom surface of the substrate to cover the opening and bond pads on the bottom surface of the substrate, disposing a die on the metal slice inside the opening or above the top surface of the substrate outside the opening, forming a number of bond wires between the top surface of the die and the top surface of the substrate to electrically connect the die to the substrate, forming an encapsulating mold compound to cover the die, the bond wires, and a part of the top surface of the substrate, removing a part of the metal slice to form a metal heat slug thermally connected to the die and to expose the bond pads, and forming a number of solder balls on the exposed bond pads.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: May 2, 2006
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Yu-Fang Tsai, Chin-Hsien Lin, Tsung-Yueh Tsai
  • Publication number: 20040161879
    Abstract: A method of manufacturing a package is disclosed. The manufacturing method includes the steps of providing a substrate having an opening, disposing a metal slice on a bottom surface of the substrate to cover the opening and bond pads on the bottom surface of the substrate, disposing a die on the metal slice inside the opening or above the top surface of the substrate outside the opening, forming a number of bond wires between the top surface of the die and the top surface of the substrate to electrically connect the die to the substrate, forming an encapsulating mold compound to cover the die, the bond wires, and a part of the top surface of the substrate, removing a part of the metal slice to form a metal heat slug thermally connected to the die and to expose the bond pads, and forming a number of solder balls on the exposed bond pads.
    Type: Application
    Filed: February 11, 2004
    Publication date: August 19, 2004
    Inventors: Yu-Fang Tsai, Chin-Hsien Lin, Tsung-Yueh Tsai
  • Publication number: 20030096473
    Abstract: A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.
    Type: Application
    Filed: November 16, 2001
    Publication date: May 22, 2003
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Wong-Cheng Shih, Wenchi Ting, Tzyh-Cheang Lee, Chin-Hsien Lin, Shyh-Chyi Wong