Patents by Inventor Chin-Hsin Chiu

Chin-Hsin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10600749
    Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 24, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chin-Hsin Chiu
  • Publication number: 20190333884
    Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chin-Hsin Chiu
  • Patent number: 10396048
    Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chin-Hsin Chiu
  • Patent number: 10199258
    Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 5, 2019
    Assignees: United Microelectronics Corp., Fujian Jianhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Hsien-Shih Chu, Ming-Feng Kuo, Fu-Che Lee, Chien-Ting Ho, Chiung-Lin Hsu, Feng-Yi Chang, Yi-Wang Zhan, Li-Chiang Chen, Chien-Cheng Tsai, Chin-Hsin Chiu
  • Publication number: 20180190603
    Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 5, 2018
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chin-Hsin Chiu
  • Publication number: 20180108563
    Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 19, 2018
    Applicants: United Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Hsien-Shih Chu, Ming-Feng Kuo, Fu-Che Lee, Chien-Ting Ho, Chiung-Lin Hsu, Feng-Yi Chang, Yi-Wang Zhan, Li-Chiang Chen, Chien-Cheng Tsai, Chin-Hsin Chiu