Abstract: An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body includes a receiving part. The receiving part is arranged at a front edge of the isolation body and has a first engaging element. The latching mechanism has a second engaging element engaged with the first engaging element, so that the latching mechanism is fixed onto the isolation body.

Abstract: An electrical connector includes a plurality of pins, an isolation body and a latching mechanism. The isolation body includes a receiving part. The receiving part is arranged at a front edge of the isolation body and has a first engaging element. The latching mechanism has a second engaging element engaged with the first engaging element, so that the latching mechanism is fixed onto the isolation body.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated package products.

Abstract: A strengthened window-type semiconductor package is provided. A substrate having an opening is mounted with at least a chip in a manner that, an active surface of the chip covers and partly exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. An elastic non-conductive material is applied over the chip exclusive of the active surface. An upper encapsulant is formed to encapsulate the chip and the non-conductive material, and a lower encapsulant is formed to encapsulate the bonding wires and seal the opening. With provision of the non-conductive material for encapsulating the chip before forming the upper encapsulant, the chip can be prevented from cracking particularly at corner and edge positions that encounter relatively greater thermal stress during subsequent fabrication processes such as curing of the upper encapsulant and thermal cycles.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated package products.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated-package products.

Abstract: A multi-chip semiconductor package and a fabrication method thereof are provided. A substrate having an upper surface and a lower surface is prepared. At least a first chip is mounted on the upper surface of the substrate. A non-conductive material is applied over predetermined area on the first chip and the upper surface of the substrate. At least a second chip is mounted on the non-conductive material, and formed with at least a suspending portion free of interference in position with the first chip, wherein the non-conductive material is dimensioned in surface area at least corresponding to the second chip, so as to allow the suspending portion to be supported on the non-conductive material. With the second chip being completely supported on the non-conductive material without causing a conventional chip-crack problem, structural intactness and reliability can be effectively assured for fabricated-package products.

Abstract: A strengthened window-type semiconductor package is provided. A substrate having an opening is mounted with at least a chip in a manner that, an active surface of the chip covers and partly exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. An elastic non-conductive material is applied over the chip exclusive of the active surface. An upper encapsulant is formed to encapsulate the chip and the non-conductive material, and a lower encapsulant is formed to encapsulate the bonding wires and seal the opening. With provision of the non-conductive material for encapsulating the chip before forming the upper encapsulant, the chip can be prevented from cracking particularly at corner and edge positions that encounter relatively greater thermal stress during subsequent fabrication processes such as curing of the upper encapsulant and thermal cycles.

Abstract: A structure facilitating easy assembly of fiber-optic communication components includes a lower and an upper support being provided with small and big V-shaped cuts, respectively, for receiving optical fibers and collimators, respectively. The upper support is inverted to seat on a middle recess of the lower support, such that tangent planes passing top points of the optical fibers and the collimators are contained in horizontal planes passing openings of the small and the big V-shaped cuts, respectively, and axes of the collimators are either in alignment with or horizontally coplanar with axes of the optical fibers. The two supports together define a central positioning cavity between them for receiving different function elements, such as optical isolator, modularized filter, etc., between the collimators, so that fiber-optic communication components with reduced volume and increased reliability could be easily assembled in mass production at reduced cost.

Abstract: A structure facilitating easy assembly of fiber-optic communication components includes a lower and an upper support being provided with small and big V-shaped cuts, respectively, for receiving optical fibers and collimators, respectively. The upper support is inverted to seat on a middle recess of the lower support, such that tangent planes passing top points of the optical fibers and the collimators are contained in horizontal planes passing openings of the small and the big V-shaped cuts, respectively, and axes of the collimators are either in alignment with or horizontally coplanar with axes of the optical fibers. The two supports together define a central positioning cavity between them for receiving different function elements, such as optical isolator, modularized filter, etc., between the collimators, so that fiber-optic communication components with reduced volume and increased reliability could be easily assembled in mass production at reduced cost.