Abstract: A device includes a biosensor, a sensing circuit electrically connected to the biosensor, a quantizer electrically connected to the sensing circuit, a digital filter electrically connected to the quantizer, a selective window electrically connected to the digital filter, and a decision unit electrically connected to the selective window.

Abstract: One or more circuit arrangements for a biosensor are provided. A circuit arrangement includes an ion sensitive sensor, a differentiator electrically connected to the ion sensitive sensor, an AC signal level comparator electrically connected to the differentiator and a decision circuit electrically connected to the AC signal level comparator. In some embodiments, the AC signal level comparator includes at least one of a first comparator or a second comparator. A method of detecting a bio-reaction is also provided.

Abstract: The present disclosure provides a device, such as a FET sensing cell, which includes a first dielectric layer over a substrate, an active layer over the first dielectric layer, a source region in the active layer, a drain region in the active layer, a channel region in the active layer situated between the source region and the drain region, a sensing film over the channel region, a second dielectric layer over the active layer, wherein an opening is formed in the second dielectric layer and the sensing film is located within the opening, a first electrode located within the second dielectric layer and a fluidic gate region located over the second dielectric layer and extending into the opening. The present disclosure also provides a method for improving the sensitivity of a device by adjusting a sensing value.

Abstract: A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout.

Abstract: One or more semiconductor devices and array arrangements and methods of formation are provided. A semiconductor device includes an ion sensing device and a heating element proximate the ion sensing device. The ion sensing device has an active region, including a source, a drain, and a channel, the channel situated between the source and the drain. The ion sensing device also has an ion sensing film situated over the channel, and an ion sensing region over the ion sensing film. Responsive to a temperature sensed by a thermal sensor proximate the ion sensing device, the heating element is selectively activated to alter a temperature of the ion sensing region to promote desired operation of the semiconductor device, such as to function as a bio sensor. Multiple semiconductor devices can be formed into an array.

Abstract: An integrated circuit includes a plurality of sensing pixels. Each sensing pixel of the plurality of sensing pixels includes a sensing film portion, a potential-sensing device configured to generate a first signal responsive to an electrical characteristic of the sensing film portion, a temperature-sensing device configured to generate a second signal responsive to a temperature of the sensing film portion, and one or more heating elements configured to adjust the temperature of the sensing film portion.

Abstract: A method for back-end-of-line variation modeling is provided. A bounding box is defined within a design layout. A back-end-of-line variation parameter is determined for the bounding box. The back-end-of-line variation parameter is applied as a constraint for simulation of the design layout.

Abstract: One or more circuit arrangements for a biosensor are provided. A circuit arrangement includes an ion sensitive sensor, a differentiator electrically connected to the ion sensitive sensor, an AC signal level comparator electrically connected to the differentiator and a decision circuit electrically connected to the AC signal level comparator. In some embodiments, the AC signal level comparator includes at least one of a first comparator or a second comparator. A method of detecting a bio-reaction is also provided.

Abstract: One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor is assigned to the device based on an architecture associated with the layout structure. When the peripheral environment is the instance, the variation factor is assigned to the device based on a bounding window created for the instance. In this manner, variation factor assignment is provided, such that a first device within a first block of a die has a different variation factor than a second device within a second block of the die, thus giving finer granularity to variation factor assignments.

Abstract: A device includes a first biosensor of a biosensor array; a second biosensor of a biosensor array; a readout circuit electrically connected to the biosensor array; a decoder electrically connected to the biosensor array; a voltage generator electrically connected to the biosensor array; and a decision system electrically connected to the voltage generator and the readout circuit.

Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.

Abstract: A device includes a biosensor, a sensing circuit electrically connected to the biosensor, a quantizer electrically connected to the sensing circuit, a digital filter electrically connected to the quantizer, a selective window electrically connected to the digital filter, and a decision unit electrically connected to the selective window.

Abstract: One or more semiconductor devices and array arrangements and methods of formation are provided. A semiconductor device includes an ion sensing device and a heating element proximate the ion sensing device. The ion sensing device has an active region, including a source, a drain, and a channel, the channel situated between the source and the drain. The ion sensing device also has an ion sensing film situated over the channel, and an ion sensing region over the ion sensing film. Responsive to a temperature sensed by a thermal sensor proximate the ion sensing device, the heating element is selectively activated to alter a temperature of the ion sensing region to promote desired operation of the semiconductor device, such as to function as a bio sensor. Multiple semiconductor devices can be formed into an array.

Abstract: The present disclosure provides a device, such as a FET sensing cell, which includes a first dielectric layer over a substrate, an active layer over the first dielectric layer, a source region in the active layer, a drain region in the active layer, a channel region in the active layer situated between the source region and the drain region, a sensing film over the channel region, a second dielectric layer over the active layer, wherein an opening is formed in the second dielectric layer and the sensing film is located within the opening, a first electrode located within the second dielectric layer and a fluidic gate region located over the second dielectric layer and extending into the opening. The present disclosure also provides a method for improving the sensitivity of a device by adjusting a sensing value.

Abstract: The present disclosure relates to a method of optimizing the area of series gate layout structures for FinFET devices. The method analyzes an integrated chip (IC) layout to determine a first gate material density along a first direction and to separately determine a second gate material density along a second direction based upon the first gate material density. A number of series gate stages for a FinFET (field effect transistor) device having a gate length along the second direction, is chosen based upon the second gate material density and one or more device performance parameters of the FinFET device. By analyzing the density of gate material in separate directions, the effective length of the gate of the FinFET can be increased without increasing the size of the transistor array.

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.

Abstract: A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract: A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.