Patents by Inventor Chin-Huang Wang
Chin-Huang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10176998Abstract: A semiconductor device includes a substrate, a dielectric layer and a floating gate. The dielectric layer disposed on the substrate. The floating gate disposed on the dielectric layer. After a first programming process, the floating gate is configured to store first electrons that are to be combined with ions from the dielectric layer. After a second programming process, the floating gate is configured to store second electrons, and a number of the second electrons is larger than a number of the first electrons.Type: GrantFiled: April 25, 2017Date of Patent: January 8, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Yu Wu, Meng-Chun Shih, Chin-Huang Wang
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Publication number: 20180308700Abstract: A semiconductor device includes a substrate, a dielectric layer and a floating gate. The dielectric layer disposed on the substrate. The floating gate disposed on the dielectric layer. After a first programming process, the floating gate is configured to store first electrons that are to be combined with ions from the dielectric layer. After a second programming process, the floating gate is configured to store second electrons, and a number of the second electrons is larger than a number of the first electrons.Type: ApplicationFiled: April 25, 2017Publication date: October 25, 2018Inventors: Chun-Yu Wu, Meng-Chun Shih, Chin-Huang Wang
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Patent number: 8194490Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.Type: GrantFiled: September 8, 2010Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hung Chen, Chin-Huang Wang, Yen-Chieh Huang, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Publication number: 20120057423Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hung CHEN, Chin-Huang WANG, Yen-Chieh HUANG, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Patent number: 7466614Abstract: A sense amplifier comprising a sense output circuit for providing a sense output signal and a logical inverse of the sense output signal based on a sense signal of a memory circuit, a charge control circuit for providing a precharge signal based on the output of the sense output circuit and a sense enable signal, a latch control circuit for providing control of a latch circuit based on the sense signal, the precharge signal and the logical inverse of the sense output signal, wherein when the sense signal is read, the latch control circuit provides one or more predetermined signals to the latch circuit to latch the sense signal to a logical level.Type: GrantFiled: October 10, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Co.Inventor: Chin-Huang Wang
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Patent number: 7462906Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.Type: GrantFiled: August 30, 2007Date of Patent: December 9, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Chin-Huang Wang
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Publication number: 20080084758Abstract: A sense amplifier comprising a sense output circuit for providing a sense output signal and a logical inverse of the sense output signal based on a sense signal of a memory circuit, a charge control circuit for providing a precharge signal based on the output of the sense output circuit and a sense enable signal, a latch control circuit for providing control of a latch circuit based on the sense signal, the precharge signal and the logical inverse of the sense output signal, wherein when the sense signal is read, the latch control circuit provides one or more predetermined signals to the latch circuit to latch the sense signal to a logical level.Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Inventor: Chin-Huang Wang
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Publication number: 20070296022Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.Type: ApplicationFiled: August 30, 2007Publication date: December 27, 2007Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Chin-Huang Wang
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Patent number: 7282410Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.Type: GrantFiled: July 21, 2004Date of Patent: October 16, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Chin-Huang Wang
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Patent number: 7257023Abstract: The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array for storing address mapping information that indicates one or more locations of one or more memory cells in the second memory cell array. The second memory cell array endures substantially more programming cycles than the first memory cell array does.Type: GrantFiled: August 10, 2005Date of Patent: August 14, 2007Inventors: Yue-Der Chih, Chin-Huang Wang
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Publication number: 20070036004Abstract: The present invention discloses a memory device that includes a first memory cell array for storing one or more codes; a second memory cell array for storing one or more data, which are updated substantially more frequently than the codes; and a third memory cell array for storing address mapping information that indicates one or more locations of one or more memory cells in the second memory cell array. The second memory cell array endures substantially more programming cycles than the first memory cell array does.Type: ApplicationFiled: August 10, 2005Publication date: February 15, 2007Inventors: Yue-Der Chih, Chin-Huang Wang
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Patent number: 7057228Abstract: This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.Type: GrantFiled: July 21, 2003Date of Patent: June 6, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yue-Der Chih, Chrong-Jung Lin, Sheng-Wei Tsao, Chin-Huang Wang
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Patent number: 7057957Abstract: This invention provides a circuit and a method for limiting the power consumed by memory array sense amplifiers while enhancing the speed of memory systems. It provides a circuit and a method which automatically limits the precharge time and voltage, which limits the power consumed and speeds the voltage transitions. The invention automatically disables the data line precharge right after achieving the trip point of the first inverter of the sense output circuit. This is the essence of the automatic saving of power consumption. In addition, the circuit and method of this invention provide for faster access speed, since the data line precharge and voltage swing are limited. Also, the circuit and method of this invention allow for smaller integrated circuit layout area due to no required reference circuit and no required circuit for generating the precharge period.Type: GrantFiled: March 26, 2004Date of Patent: June 6, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Chin-Huang Wang
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Publication number: 20060019444Abstract: A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.Type: ApplicationFiled: July 21, 2004Publication date: January 26, 2006Inventors: Hsiang-Tai Lu, Cheng-Hsiung Kuo, Chin-Huang Wang
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Patent number: 6958939Abstract: A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.Type: GrantFiled: September 15, 2003Date of Patent: October 25, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ta Hsieh, Chin-Huang Wang, I-Ming Chang, Hsiang-Tai Lu
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Publication number: 20050213406Abstract: This invention provides a circuit and a method for limiting the power consumed by memory array sense amplifiers while enhancing the speed of memory systems. It provides a circuit and a method which automatically limits the precharge time and voltage, which limits the power consumed and speeds the voltage transitions. The invention automatically disables the data line precharge right after achieving the trip point of the first inverter of the sense output circuit. This is the essence of the automatic saving of power consumption. In addition, the circuit and method of this invention provide for faster access speed, since the data line precharge and voltage swing are limited. Also, the circuit and method of this invention allow for smaller integrated circuit layout area due to no required reference circuit and no required circuit for generating the precharge period.Type: ApplicationFiled: March 26, 2004Publication date: September 29, 2005Inventor: Chin-Huang Wang
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Publication number: 20050057971Abstract: A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.Type: ApplicationFiled: September 15, 2003Publication date: March 17, 2005Inventors: Chia-Ta Hsieh, Chin-Huang Wang, I-Ming Chang, Hsiang-Tai Lu
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Publication number: 20050017287Abstract: This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.Type: ApplicationFiled: July 21, 2003Publication date: January 27, 2005Inventors: Yue-Der Chih, Chrong-Jung Lin, Sheng-Wei Tsao, Chin-Huang Wang