Abstract: A FinFET including a substrate, a plurality of isolators, a gate stack, and strained material portions is provided. The substrate includes at least two fins thereon. The isolators are disposed on the substrate, and each of the insulators between the fins has a recess profile. The gate stack is disposed over portions of the fins and over the insulators. The strained material portions cover the fins revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.

Abstract: A method of fabricating a FinFET includes at last the following steps. A semiconductor substrate is patterned to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin between the trenches. Insulators are formed in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. A strained material doped with a conductive dopant is formed over portions of the semiconductor fin revealed by the gate stack, and the strained material is formed by selectively growing a bulk layer with a gradient doping concentration.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate; a gate structure over a fin structure of the semiconductive substrate; a channel portion of the fin structure under the gate structure; and at least one epitaxy region disposed over the semiconductive substrate and in contact with the channel portion. The epitaxy region includes a substance with a first lattice constant larger than a second lattice constant of the semiconductive substrate; and a concentration profile of the substance in the epitaxy region being decreasing from near a bottom portion to near a top portion. The bottom portion is closer to the channel portion than the top portion.

Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.

Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.

Abstract: The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top surface of the insulation region; a gate over the semiconductor fin; and a regrowth region partially positioned in the semiconductor fin, and the regrowth region forming a source/drain region of the semiconductor structure; wherein a profile of the regrowth region taken along a plane perpendicular to a direction of the semiconductor fin and top surfaces of the insulation region includes a girdle, an upper girdle facet facing away from the insulation region, and a lower girdle facet facing toward the insulation region, and an angle between the upper girdle facet and the girdle is greater than about 54.7 degrees.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate; a gate structure over a fin structure of the semiconductive substrate; a channel portion of the fin structure under the gate structure; and at least one epitaxy region disposed over the semiconductive substrate and in contact with the channel portion. The epitaxy region includes a substance with a first lattice constant larger than a second lattice constant of the semiconductive substrate; and a concentration profile of the substance in the epitaxy region being decreasing from near a bottom portion to near a top portion. The bottom portion is closer to the channel portion than the top portion.

Abstract: A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures spaced apart from each other are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure. The cap simultaneously surrounds the epitaxial structures, and at least two adjacent caps are merged together.

Abstract: A method for fabricating a semiconductor device is described. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion. A semiconductor device is also described, which includes the spacer, the remaining fin structure and the semiconductor layer that are mentioned above.

Abstract: A method for fabricating a semiconductor device is described. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion. A semiconductor device is also described, which includes the spacer, the remaining fin structure and the semiconductor layer that are mentioned above.

Abstract: An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 <1,1,1> surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided.

Abstract: A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect.

Abstract: A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures spaced apart from each other are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure. The cap simultaneously surrounds the epitaxial structures, and at least two adjacent caps are merged together.

Abstract: A manufacturing method of a semiconductor device is provided. The method includes at least the following steps. A gate structure is formed on a substrate. An epitaxial structure is formed on the substrate, wherein the epitaxial structure comprises SiGe, and the Ge concentration in the epitaxial structure is equal to or higher than 45%. A first cap layer is formed on the epitaxial structure, wherein the first cap layer comprises Si. The first cap layer is doped with boron for forming a flat top surface of the first cap layer.

Abstract: A fin structure includes a substrate and a fin disposed on a top surface of the substrate. The fin has a height. An epitaxial structure surrounds the fin and the epitaxial structure has a top point which is the farthest point on the epitaxial structure away from the top surface of the substrate. There is a distance between the top point and the top surface of the substrate. A rational number of the distance to the height is not less than 7.

Abstract: An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 <1,1,1> surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided.

Abstract: A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other. The silicon cap simultaneously surrounds the epitaxial structures.

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract: A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.