Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: A method of operating a memory circuit includes generating, by a first memory cell array, a first current in response to a first voltage, generating, by a tracking circuit, a second set of leakage currents, generating, by a first current source, a second write current, and mirroring, by a first current mirror. The first current includes a first set of leakage currents and a first write current. The first current is in a first path with a second current in a second path. The second current includes the second set of leakage currents and the second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents. The second set of leakage currents is configured to track the first set of leakage currents of the first memory cell array.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.

Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: An optoelectronic semiconductor device is provided. The optoelectronic semiconductor device includes a substrate, a semiconductor stack located on the substrate; a first trench and a second trench provided in the semiconductor stack; a first insulating layer filling in the first trench and covering the semiconductor stack; a first metal layer covering the first insulating layer; a second metal layer covering the first insulating layer; and a second insulating layer located between the first metal layer and the first insulating layer, and between the second metal layer and the first insulating layer. A part of the second trench is uncovered by the first insulating layer and the second insulating layer.

Abstract: A magnetic nanoparticle is provided in the disclosure. The magnetic nanoparticle includes a magnetic nanoparticle; a biocompatible polymer of the following formula (II) covalently coupled to the magnetic nanoparticle, wherein R1 is alkyl, aryl, carboxyl, or amino; n is an integer from 5 to 1000; and m is an integer from 1 to 10.

Abstract: A thermosensitive nanostructure for hyperthermia treatment. Magnetic nanoparticles are encapsulated in a thermosensitive polymer nanostructure having a lower critical solution temperature (LCST) of about 40-45° C. The thermosensitive polymer nanostructure may carry a drug. When the magnetic nanoparticles are heated to 40-45° C. by application of an alternating magnetic field in hyperthermia treatment, the thermosensitive polymer nanostructure collapses to release the drug, thus providing concurrent drug treatment.

Abstract: A dendritic polymer and a magnetic resonance imaging contrast agent employing the same. The magnetic resonance contrast agent includes the dendritic polymer according to the structure of SP-DZ-L)i)j or SP-DX-Z-L)i)j, wherein, S is cyclosilane moiety with j silicon oxygen residual groups, and j is not less than 2; P is CH2CH2Ol, and l is not less than 1; D is a C3-30 dendritic moiety having n oxygen residue, and n is not less than 3; X is C3-30 moiety having bi-functional groups; Z is a C3-20 moiety having a plurality of functional group; and L is a metal cation.

Abstract: A magnetic nanoparticle is provided in the disclosure. The magnetic nanoparticle includes a magnetic nanoparticle; a biocompatible polymer of the following formula (II) covalently coupled to the magnetic nanoparticle, wherein R1 is alkyl, aryl, carboxyl, or amino; n is an integer from 5 to 1000; and m is an integer from 1 to 10.

Abstract: A dendritic polymer and a magnetic resonance imaging contrast agent employing the same. The magnetic resonance contrast agent includes the dendritic polymer according to the structure of SP-DZ-L)i)j or SP-DX-Z-L)i)j, wherein, S is cyclosilane moiety with j silicon oxygen residual groups, and j is not less than 2; P is and l is not less than 1; D is a C3-30 dendritic moiety having n oxygen residue, and n is not less than 3; X is C3-30 moiety having bi-functional groups; Z is a C3-20 moiety having a plurality of functional group; and L is a metal cation.

Abstract: A hair growth agent having an effective dose of a platelet dry powder and a pharmaceutically acceptable solvent and/or excipient, wherein the effective dose refers to the presence of at least 1,000 platelets in every milligram of the hair growth agent.

Abstract: A core-shell structure with magnetic, thermal, and optical characteristics. The optical absorption band is tailorable by choice of the mixing ratio of the core/shell component to give the desired shell thickness. The core-shell structure is particularly suitable for biomedical applications such as MRI (magnetic resonance imaging) developer, specific tissue identification developer, and magnetic thermal therapy.

Abstract: A dendritic polymer and a magnetic resonance imaging contrast agent employing the same. The magnetic resonance contrast agent includes the dendritic polymer according to the structure of wherein, P is ?CH2CH2O?1, and 1 is not less than 1 and j is not less than 2; D is a C3-30 dendritic moiety having n oxygen residue, and n is not less than 3 and i is more than 1; X is C3-30 moiety having bi-functional groups; Z is independent and includes a C3-20 moiety having a plurality of functional group, wherein the functional groups are selected from a group consisting of carbonyl, carboxyl, amine, ester, amide, or chelate group, and Z respectively bonds with X by a group; and L is a metal cation.

Abstract: A dendritic polymer and a magnetic resonance imaging contrast agent employing the same. The magnetic resonance contrast agent includes the dendritic polymer according to the structure of S?P-D?Z-L)i)j or S?P-D?X-Z-L)i)j, wherein, S is cyclosilane moiety with j silicon oxygen residual groups, and j is not less than 2; P is and 1 is not less than 1; D is a C3-30 dendritic moiety having n oxygen residue, and n is not less than 3; X is C3-30 moiety having bi-functional groups; Z is a C3-20 moiety having a plurality of functional group; and L is a metal cation.

Abstract: A biochemical labeling material and manufacturing method thereof. The manufacturing method provides a plurality of nanoparticles, bonding the nanoparticles to template molecules by molecular imprinting, polymerizing the nanoparticles to form a matrix with uniformly-distributed template molecules, finally removing the template molecules from the matrix to reveal a detection group of the matrix, leaving a cavity with specific area.