Patents by Inventor Chin-I Su
Chin-I Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240036597Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
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Publication number: 20230377648Abstract: A method of operating a memory circuit includes generating a first current in response to a first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Publication number: 20230335189Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
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Patent number: 11735263Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.Type: GrantFiled: July 22, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
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Publication number: 20230253041Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.Type: ApplicationFiled: April 20, 2023Publication date: August 10, 2023Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Patent number: 11715518Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.Type: GrantFiled: September 9, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
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Patent number: 11636896Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.Type: GrantFiled: November 24, 2020Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
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Publication number: 20220359010Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Patent number: 11442482Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.Type: GrantFiled: September 2, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
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Publication number: 20220254412Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.Type: ApplicationFiled: September 9, 2021Publication date: August 11, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
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Publication number: 20210407594Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.Type: ApplicationFiled: November 24, 2020Publication date: December 30, 2021Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Publication number: 20210096586Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.Type: ApplicationFiled: September 2, 2020Publication date: April 1, 2021Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su