Patents by Inventor Chin Keat Teoh

Chin Keat Teoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10139445
    Abstract: A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Chin Keat Teoh, Satheesh Chellappan, Lay Cheng Ong, Terrence Huat Hin Tan
  • Publication number: 20180096736
    Abstract: A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Chin Keat Teoh, Satheesh Chellappan, Lay Cheng Ong, Terrence Huat Hin Tan