Patents by Inventor Chin-Kuan Liu

Chin-Kuan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11044806
    Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 22, 2021
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Publication number: 20200128662
    Abstract: A manufacturing method for a multi-layer circuit board capable of being applied with electrical testing is provided. According to the multi-layer circuit board manufactured by the method, the multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Patent number: 10548214
    Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 28, 2020
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Patent number: 10455694
    Abstract: A manufacturing method for a multi-layer circuit board is provided. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 22, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Publication number: 20190269008
    Abstract: A manufacturing method for a multi-layer circuit board is provided. According to the multi-layer circuit board manufactured by the manufacturing method, the multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Patent number: 10334719
    Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Publication number: 20190059153
    Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.
    Type: Application
    Filed: November 30, 2017
    Publication date: February 21, 2019
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Publication number: 20190059154
    Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer.
    Type: Application
    Filed: November 30, 2017
    Publication date: February 21, 2019
    Inventors: Chin-Kuan Liu, Chao-Lung Wang, Shuo-Hsun Chang, Yu-Te Lu, Chin-Hsi Chang
  • Publication number: 20090225524
    Abstract: A method for forming a via hole in a hollowed PCB, which has a hollow portion and at least one insulating layer, includes the steps of: providing a lining pad on a first surface of the insulating layer that is adjacent to the hollow portion; drilling the via hole in the insulating layer from a second surface of the insulating layer that is opposite to the first surface of the insulating layer. In such a way, when the insulating layer is drilled to form the via hole, the insulating layer is supported by the lining pad, thereby preventing the defects, such as burrs, cracks, or pads, from occurring.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 10, 2009
    Inventors: Chin-Kuan Liu, Chun-Hong Liu