Patents by Inventor Chin Liang

Chin Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250255080
    Abstract: The present disclosure provides an optoelectronic device including a base, a light-emitting chip, an interposer, a wavelength conversion member and a wall portion. The base includes a base portion and a conductive portion, and the conductive portion comprises a plurality of coupling surfaces. The base portion covers the conductive portion and exposes the coupling surfaces. The light-emitting chip and the interposer are provided on the base, and having a top surface. The interposer covers the light-emitting chip and exposes the top surface. The wavelength conversion member covers the light-emitting chip and the interposer, and the wavelength conversion member includes an emitting surface. The wall portion is provided on the base. The wall portion covers the interposer and the wavelength conversion member, and exposes the emitting surface of the wavelength conversion member. The emitting surface is parallel to the top surface, and perpendicular to the coupling surfaces.
    Type: Application
    Filed: January 2, 2025
    Publication date: August 7, 2025
    Inventors: Shiou-Yi KUO, Jian-Chin LIANG
  • Patent number: 12347802
    Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Yu Chen, Chi-Yang Yu, Kuan-Lin Ho, Chin-Liang Chen, Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20250081419
    Abstract: The present disclosure provides a display case. The display case includes a central portion having an inlet and an outlet opposite to the inlet, a first transparent lid disposed on a first side of the central portion, a second transparent lid disposed on a second side of the central portion, and a heat exchanger in the central portion. The first transparent lid is configured to define a first space on the first side of the central portion and the second transparent lid is configured to define a second space on the second side of the central portion. The heat exchanger includes a first channel and a second channel. The first channel of the heat exchanger is fluidly conducted to the first space and defines a part of a first internal heat exchange loop. The second channel of the heat exchanger is fluidly conducted to the second space and defines a part of a second internal heat exchange loop. The present disclosure also provides a dual sided display.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Inventors: Ching-Chun Wu, Chia-Liang Yang, Chin Liang Wang
  • Publication number: 20250062184
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
  • Patent number: 12165946
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
  • Publication number: 20240395986
    Abstract: A light-emitting element, a manufacturing method thereof, and a package structure are provided. The light-emitting element includes a first semiconductor layer, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and a convex lens structure disposed on the second semiconductor layer. The convex lens structure includes a plurality of microlenses. The microlenses and the second semiconductor layer are integrally formed and have the same material. The radius of curvature of one of the microlenses is 0.2 ?m to 5.0 ?m, and the light-emission angle of the light-emitting element is 100° to 110°.
    Type: Application
    Filed: May 20, 2024
    Publication date: November 28, 2024
    Inventors: Shiou-Yi KUO, Jian-Chin LIANG, Cheng-Hsien LI, Kai Hung CHENG
  • Publication number: 20240394069
    Abstract: A method for accessing a BMC using a playbook includes steps of: receiving from an initiator a playbook that includes to-be-executed instructions, a plurality of execution durations, a summarizing instruction, and a series of storing instructions; in response to receiving the playbook, the BMC executing the to-be-executed instructions; the BMC generating an execution result related to the to-be-executed instructions after executing the to-be-executed instructions; after generating the execution result, the BMC executing the summarizing instruction and summarizing the execution result according to a predetermined summarizing manner to obtain a summarizing result; and, after obtaining the summarizing result, the BMC executing the series of storing instructions and storing the execution result and the summarizing result according to a predetermined storing manner.
    Type: Application
    Filed: March 25, 2024
    Publication date: November 28, 2024
    Applicant: Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Cheng-Huang Wang, Chin Liang, Jung-Te Chou
  • Publication number: 20240387457
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a conductive terminal. The first die includes a first connector, and the second die includes a second connector. The first encapsulant includes: a first portion, on the second die; a second portion, sandwiched between a first sidewall of the first die and a first sidewall of the second die; and a third portion, covering a second sidewall of the second die. The second encapsulant, laterally encapsulating the first die, the second die and the first encapsulant. The conductive terminal, electrically connected to the first die and the second die through a redistribution layer (RDL) structure. The third portion of first encapsulant is sandwiched between the second sidewall of the second die and the second encapsulant.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Chien-Hsun Lee, Kuan-Lin Ho, Yu-Min Liang
  • Publication number: 20240363544
    Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chin-Liang Chen, Jiun-Yi Wu, Yen-Ping Wang
  • Publication number: 20240321759
    Abstract: A package structure includes an interposer including a front side and a back side opposite the front side, an upper molded structure on the front side of the interposer and including an upper molding layer and a semiconductor die in the upper molding layer, and a lower molded structure on the back side of the interposer and including a lower molding layer and a substrate portion in the lower molding layer, wherein the substrate portion includes conductive layers electrically coupled to the semiconductor die through the interposer.
    Type: Application
    Filed: June 30, 2023
    Publication date: September 26, 2024
    Inventors: Tsung-Ding Wang, Chien-Hsun Lee, Shang-Yun Hou, Hao-Cheng Hou, Chin-Liang Chen
  • Patent number: 12094861
    Abstract: Disclosed is a light-emitting array structure having a substrate, a plurality of light-emitting pixel units, a plurality of first and second signal wires, and an encapsulating layer. The light-emitting pixel units are arranged in array on the substrate. Each light-emitting pixel unit includes a driving chip, a first flat layer, a first redistribution layer, a second flat layer, a second redistribution layer, and a light-emitting diode. Each first signal wire is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction. The second signal wires extend in a level different from the first signal wires. Each second signal wire is electrically connected to a corresponding one of the second redistribution layers and extends in a second direction different from the first direction. The encapsulating layer covers the light-emitting pixel units, the first and second signal wires, and the substrate.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 17, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jian-Chin Liang, Chien-Nan Yeh, Shih-Lun Lai, Jo-Hsiang Chen
  • Patent number: 12088731
    Abstract: A program signing method is provided to include: determining whether the signing program is tampered with; if not, obtaining a releasing hash that is related to a to-be-released program, and transmitting the releasing hash to a signature server unit, so as to make the signature server unit acquire a releasing digital signature based on the releasing hash and transmit the releasing digital signature to the processing module; and, upon receipt of the releasing digital signature, executing the signing program to generate a signed to-be-released program.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: September 10, 2024
    Assignee: Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Cheng Huang Wang, Chin Liang, Shuo-Hung Hsu
  • Patent number: 12062619
    Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chin-Liang Chen, Jiun-Yi Wu, Yen-Ping Wang
  • Patent number: 12062604
    Abstract: A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
  • Publication number: 20240204159
    Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Inventors: Chih-Hao LIN, Jian-Chin LIANG, Shih-Lun LAI, Jo-Hsiang CHEN
  • Publication number: 20240194848
    Abstract: The light emitting diode packaging structure includes a flexible substrate, micro light emitting elements disposed on the flexible substrate, a conductive pad, a redistribution layer, and an electrode pad. The micro light emitting elements have a first surface facing to the flexible substrate and a second surface opposite to the first surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting elements. The redistribution layer covers the micro light emitting elements and the conductive pad. The redistribution layer includes an insulating layer and a circuit layer embedded in the insulating layer. The circuit layer is electrically connected to the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer.
    Type: Application
    Filed: February 27, 2024
    Publication date: June 13, 2024
    Inventors: Chih-Hao LIN, Jo-Hsiang CHEN, Shih-Lun LAI, Min-Che TSAI, Jian-Chin LIANG
  • Publication number: 20240177653
    Abstract: A light-emitting diode (LED) display device, includes: a plurality of displaying basic-units, each of the displaying basic-units having a plurality of sub-pixel regions, on which a plurality of red LED units, a plurality of green LED units, a plurality of blue LED units, and a plurality of white LED units are selectively provided; and a control unit, performing an image reconstruction process for an input image, thereby making each of the displaying basic-units display color, color grayscale, or black-and-white grayscale; wherein in each of the displaying basic-units, the quantity of green LED units is more than or equal to the quantity of white LED units, and the quantity of green LED units is more than the quantity of blue LED units or red LED units.
    Type: Application
    Filed: September 28, 2023
    Publication date: May 30, 2024
    Inventors: Jui Yi WU, Chih Hao LIN, Jian-Chin LIANG
  • Patent number: 11972956
    Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
  • Patent number: 11961951
    Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: April 16, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jian-Chin Liang, Shih-Lun Lai, Jo-Hsiang Chen
  • Patent number: 11949056
    Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 2, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jo-Hsiang Chen, Shih-Lun Lai, Min-Che Tsai, Jian-Chin Liang