Patents by Inventor Chin-Lung Chu
Chin-Lung Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10923455Abstract: The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.Type: GrantFiled: December 4, 2018Date of Patent: February 16, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Patent number: 10825794Abstract: The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.Type: GrantFiled: August 31, 2018Date of Patent: November 3, 2020Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Semiconductor method for forming semiconductor structure having bump on tilting upper corner surface
Patent number: 10607858Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.Type: GrantFiled: November 7, 2018Date of Patent: March 31, 2020Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu -
Patent number: 10566294Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.Type: GrantFiled: November 28, 2018Date of Patent: February 18, 2020Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Patent number: 10446514Abstract: A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.Type: GrantFiled: July 30, 2018Date of Patent: October 15, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Patent number: 10373932Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.Type: GrantFiled: April 20, 2017Date of Patent: August 6, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Patent number: 10290512Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.Type: GrantFiled: May 17, 2017Date of Patent: May 14, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Publication number: 20190122996Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.Type: ApplicationFiled: November 28, 2018Publication date: April 25, 2019Inventors: Po-Chun LIN, Chin-Lung CHU
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Publication number: 20190109113Abstract: The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.Type: ApplicationFiled: December 4, 2018Publication date: April 11, 2019Inventors: Po-Chun LIN, Chin-Lung CHU
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SEMICONDUCTOR METHOD FOR FORMING SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE
Publication number: 20190074197Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.Type: ApplicationFiled: November 7, 2018Publication date: March 7, 2019Inventors: Po-Chun LIN, Chin-Lung CHU -
Patent number: 10192853Abstract: The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.Type: GrantFiled: December 22, 2017Date of Patent: January 29, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Patent number: 10170432Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure is used to be electrically connected to a power terminal or a ground terminal.Type: GrantFiled: April 20, 2017Date of Patent: January 1, 2019Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Publication number: 20180374818Abstract: The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.Type: ApplicationFiled: August 31, 2018Publication date: December 27, 2018Inventors: PO-CHUN LIN, CHIN-LUNG CHU
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Publication number: 20180337154Abstract: A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Po-Chun LIN, Chin-Lung CHU
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Publication number: 20180337116Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.Type: ApplicationFiled: May 17, 2017Publication date: November 22, 2018Inventors: Po-Chun LIN, Chin-Lung CHU
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Publication number: 20180315725Abstract: A package structure includes a semiconductor substrate: a pad disposed on the semiconductor substrate; a conductive layer disposed on the pad; a protection coating; and a metal bump disposed on the conductive layer, and the metal bump covered with the protection coating so as to avoid oxidation of the metal bump.Type: ApplicationFiled: April 26, 2017Publication date: November 1, 2018Inventors: Po-Chun LIN, Chin-Lung CHU
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Publication number: 20180308823Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Inventors: Po-Chun LIN, Chin-Lung CHU
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Publication number: 20180308803Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure is used to be electrically connected to a power terminal or a ground terminal.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Inventors: Po-Chun LIN, Chin-Lung CHU
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Patent number: 10068865Abstract: A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on the semiconductor substrate. The conductive layer is disposed on the pad. The solder bump is disposed on the conductive layer. The at least two metal side walls are disposed along opposing outer side walls of the solder bump respectively.Type: GrantFiled: May 10, 2017Date of Patent: September 4, 2018Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Po-Chun Lin, Chin-Lung Chu
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Publication number: 20180233484Abstract: A semiconductor structure includes a first die; a second die disposed over or at least partially in contact with the first die; a redistribution layer (RDL) disposed over the second die; a conductive pillar extended between the first die and the RDL; and a molding surrounding the first die, the second die and the conductive pillar, wherein the first die and the RDL are electrically connected by the conductive pillar.Type: ApplicationFiled: February 14, 2017Publication date: August 16, 2018Inventors: PO-CHUN LIN, CHIN-LUNG CHU