Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.

Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.

Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.

Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.

Abstract: A sensing apparatus that includes a plurality of sensing pixels is provided. The sensing pixels are arranged in an array, and each of the sensing pixels includes an active device and a sensing device. The sensing device is electrically connected to the active device, and the sensing device includes a first electrode layer, an amorphous silicon layer, a second electrode layer, and a graphene layer. The amorphous silicon layer is located on the first electrode layer. The second electrode layer is located on the amorphous silicon layer and has an opening. The graphene layer is in contact with the second electrode layer and the amorphous silicon layer.

Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.

Abstract: The present invention provides a manufacturing method of an image TFT array, which includes providing a substrate including a thin film transistor region, a storage capacitor region, a pad region, and a common electrode region, forming a photoresist layer on the substrate, and performing a photolithographic and etching process by utilizing a half-tone mask to pattern the photoresist layer to define a position of a through hole on the storage capacitor region and form the photoresist layer of a first thickness on the thin film transistor region and the photoresist layer of a second thickness on the region between the thin film transistor region and the storage capacitor region, wherein the first thickness is greater than the second thickness.

Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

Abstract: The present invention provides a manufacturing method of an image TFT array, which includes providing a substrate including a thin film transistor region, a storage capacitor region, a pad region, and a common electrode region, forming a photoresist layer on the substrate, and performing a photolithographic and etching process by utilizing a half-tone mask to pattern the photoresist layer to define a position of a through hole on the storage capacitor region and form the photoresist layer of a first thickness on the thin film transistor region and the photoresist layer of a second thickness on the region between the thin film transistor region and the storage capacitor region, wherein the first thickness is greater than the second thickness.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.

Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

Abstract: A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.

Abstract: A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.