Patents by Inventor Chin-Mao Lin

Chin-Mao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200091029
    Abstract: A package structure and method for forming the same are provided. The package structure includes a semiconductor die formed over a first side of an interconnect structure, and the semiconductor die has a first height. The package structure also includes a first stacked die package structure formed over the first side of the interconnect structure, and the first stacked die package structure has a second height. The second height is greater than the first height. The package structure includes a lid structure formed over the semiconductor die and the first stacked die package structure. The lid includes a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 19, 2020
    Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
  • Patent number: 10323332
    Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 18, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
  • Patent number: 9653505
    Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 16, 2017
    Assignee: Au Optronics Corporation
    Inventors: Te-Ming Chen, Chin-Mao Lin
  • Publication number: 20160172400
    Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Inventors: Te-Ming Chen, Chin-Mao Lin
  • Patent number: 9312423
    Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: April 12, 2016
    Assignee: Au Optronics Corporation
    Inventors: Te-Ming Chen, Chin-Mao Lin
  • Patent number: 9190446
    Abstract: A sensing apparatus that includes a plurality of sensing pixels is provided. The sensing pixels are arranged in an array, and each of the sensing pixels includes an active device and a sensing device. The sensing device is electrically connected to the active device, and the sensing device includes a first electrode layer, an amorphous silicon layer, a second electrode layer, and a graphene layer. The amorphous silicon layer is located on the first electrode layer. The second electrode layer is located on the amorphous silicon layer and has an opening. The graphene layer is in contact with the second electrode layer and the amorphous silicon layer.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: November 17, 2015
    Assignee: Au Optronics Corporation
    Inventors: Tsung-Han Chen, Chin-Mao Lin
  • Publication number: 20140346517
    Abstract: A photo detector and a method for fabricating the same are provided. The photo detector includes a first substrate and a photo conversion element. The first substrate has a sensor element array for receiving a light with a spectrum in a specific wavelength range. The photo conversion element is disposed on the sensor element array, where the photo conversion element includes a photo conversion material layer and a doped photo conversion material column structure layer. A luminescent spectrum of the doped photo conversion material layer column structure layer is overlapped with the spectrum in a specific wavelength range, and a luminescent spectrum of the photo conversion material layer is non-overlapped with the spectrum in a specific wavelength range.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: Au Optronics Corporation
    Inventors: Te-Ming Chen, Chin-Mao Lin
  • Patent number: 7439544
    Abstract: The present invention provides a manufacturing method of an image TFT array, which includes providing a substrate including a thin film transistor region, a storage capacitor region, a pad region, and a common electrode region, forming a photoresist layer on the substrate, and performing a photolithographic and etching process by utilizing a half-tone mask to pattern the photoresist layer to define a position of a through hole on the storage capacitor region and form the photoresist layer of a first thickness on the thin film transistor region and the photoresist layer of a second thickness on the region between the thin film transistor region and the storage capacitor region, wherein the first thickness is greater than the second thickness.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 21, 2008
    Assignee: HannStar Display Corp.
    Inventors: Chin-Mao Lin, Kei-Hsiung Yang, Chian-Chih Hsiao
  • Patent number: 7145172
    Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: December 5, 2006
    Assignee: Hannstar Display Corporation
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20060183263
    Abstract: The present invention provides a manufacturing method of an image TFT array, which includes providing a substrate including a thin film transistor region, a storage capacitor region, a pad region, and a common electrode region, forming a photoresist layer on the substrate, and performing a photolithographic and etching process by utilizing a half-tone mask to pattern the photoresist layer to define a position of a through hole on the storage capacitor region and form the photoresist layer of a first thickness on the thin film transistor region and the photoresist layer of a second thickness on the region between the thin film transistor region and the storage capacitor region, wherein the first thickness is greater than the second thickness.
    Type: Application
    Filed: April 25, 2005
    Publication date: August 17, 2006
    Inventors: Chin-Mao Lin, Kei-Hsiung YANG, Chian-Chih Hsiao
  • Patent number: 7087469
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 8, 2006
    Assignee: Hannstar Display Corp.
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Patent number: 6953715
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: October 11, 2005
    Assignee: HannStar Display Corporation
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20050037533
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.
    Type: Application
    Filed: September 3, 2004
    Publication date: February 17, 2005
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20050032263
    Abstract: A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.
    Type: Application
    Filed: September 3, 2004
    Publication date: February 10, 2005
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20050023533
    Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
    Type: Application
    Filed: September 2, 2004
    Publication date: February 3, 2005
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Patent number: 6800510
    Abstract: A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: October 5, 2004
    Assignee: HannStar Display Corporation
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin
  • Publication number: 20040084678
    Abstract: A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin