Patents by Inventor Chin Min Huang
Chin Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11748549Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: GrantFiled: April 21, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Publication number: 20230267266Abstract: A method for forming a photomask includes following operations. A first photomask is received. The first photomask includes a first pattern and a first scattering bar. The first photomask is used to remove a first portion of a target layer to form a first opening and a second opening. The first opening corresponds to the first pattern, and the second opening corresponds to the first scattering bar. A second photomask is received. The second photomask includes a second pattern. The second photomask is used to remove a second portion of the target layer to form a third opening. The third opening corresponds to the second pattern. The second opening is widened to form the third opening using the second photomask.Type: ApplicationFiled: April 25, 2023Publication date: August 24, 2023Inventors: CHIN-MIN HUANG, CHING-HUNG LAI, JIA-GUEI JOU, YIN-CHUAN CHEN, CHI-MING TSAI
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Patent number: 11669670Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout, the initial layout comprising a first pattern and a second pattern; decomposing the initial layout into a first layout including the first pattern and a second layout including the second pattern; inserting a third pattern into the first layout; overlapping the first layout including the first pattern and the third pattern to the second layout including the second pattern; increasing a width of the third pattern in the first layout overlapping the second pattern in the second layout to form a fourth pattern in the first layout; and outputting the first layout comprising the first pattern, the third pattern and the fourth pattern into a first photomask.Type: GrantFiled: December 8, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Min Huang, Ching-Hung Lai, Jia-Guei Jou, Yin-Chuan Chen, Chi-Ming Tsai
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Patent number: 11622263Abstract: A wireless repeater device and a configuration method for the same are provided. The wireless repeater device is configured to: connect to a target network provided by a DHCP server; send a detection packet to the target network to confirm transmission modes supported by the DHCP server; confirm whether a request for dynamically obtaining an IP address from a client device is received; forward a request packet to the DHCP server, which instructs the DHCP server to respond in a first transmission mode; receive a response to the request from the DHCP server and forward it to the client device; confirm whether the request from the client device is still received, if so, modify the request packet and forward it to the DHCP server, and the request packet is modified to instruct the DHCP server to respond in a second transmission mode.Type: GrantFiled: June 22, 2021Date of Patent: April 4, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chin-Min Huang, Chin-Yu Hsu
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Publication number: 20220159454Abstract: A wireless repeater device and a configuration method for the same are provided. The wireless repeater device is configured to: connect to a target network provided by a DHCP server; send a detection packet to the target network to confirm transmission modes supported by the DHCP server; confirm whether a request for dynamically obtaining an IP address from a client device is received; forward a request packet to the DHCP server, which instructs the DHCP server to respond in a first transmission mode; receive a response to the request from the DHCP server and forward it to the client device; confirm whether the request from the client device is still received, if so, modify the request packet and forward it to the DHCP server, and the request packet is modified to instruct the DHCP server to respond in a second transmission mode.Type: ApplicationFiled: June 22, 2021Publication date: May 19, 2022Inventors: CHIN-MIN HUANG, CHIN-YU HSU
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Publication number: 20210240907Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: ApplicationFiled: April 21, 2021Publication date: August 5, 2021Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Patent number: 10990744Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: GrantFiled: January 11, 2018Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Publication number: 20210089701Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout, the initial layout comprising a first pattern and a second pattern; decomposing the initial layout into a first layout including the first pattern and a second layout including the second pattern; inserting a third pattern into the first layout; overlapping the first layout including the first pattern and the third pattern to the second layout including the second pattern; increasing a width of the third pattern in the first layout overlapping the second pattern in the second layout to form a fourth pattern in the first layout; and outputting the first layout comprising the first pattern, the third pattern and the fourth pattern into a first photomask.Type: ApplicationFiled: December 8, 2020Publication date: March 25, 2021Inventors: CHIN-MIN HUANG, CHING-HUNG LAI, JIA-GUEI JOU, YIN-CHUAN CHEN, CHI-MING TSAI
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Patent number: 10867107Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.Type: GrantFiled: September 25, 2018Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Min Huang, Ching-Hung Lai, Jia-Guei Jou, Yin-Chuan Chen, Chi-Ming Tsai
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Publication number: 20200097631Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: CHIN-MIN HUANG, CHING-HUNG LAI, JIA-GUEI JOU, YIN-CHUAN CHEN, CHI-MING TSAI
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Publication number: 20180184469Abstract: A method for wirelessly connecting to an internet, applied for establishing a wireless connection between a mobile device and a plurality of wireless networking devices, the method including: the mobile device searching for the plurality of wireless networking devices via a wireless communication; the mobile device wirelessly connecting with a main controlling device which is one of the plurality of wireless networking devices; the mobile device providing a connection information to the main controlling device for connecting to a base station; and the main controlling device broadcasting the connection information to the other wireless networking devices of the plurality of wireless networking devices; and the main controlling device and the other wireless networking devices of the plurality of wireless networking devices connecting to the base station according to the connection information.Type: ApplicationFiled: December 28, 2017Publication date: June 28, 2018Inventors: CHIN-MIN HUANG, MENG-SHIN LEE, KAI-CHUN LIN, CHI-SHENG WANG
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Publication number: 20180137233Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Patent number: 9870443Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.Type: GrantFiled: November 23, 2015Date of Patent: January 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Publication number: 20160085906Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.Type: ApplicationFiled: November 23, 2015Publication date: March 24, 2016Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
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Patent number: 9213233Abstract: Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process.Type: GrantFiled: July 12, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Cheng Chang, Wei-Kuan Yu, Yen-Hsu Chu, Tsai-Ming Huang, Chin-Min Huang, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin
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Patent number: 9195134Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.Type: GrantFiled: August 1, 2013Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Min Huang, Bo-Han Chen, Lun-Wen Yeh, Shun-Shing Yang, Chia-Cheng Chang, Chern-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin
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Patent number: 9026956Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.Type: GrantFiled: October 11, 2013Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Cheng Chang, Wei-Kuan Yu, Tsai-Ming Huang, Chin-Min Huang, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Shih-Ming Chang
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Publication number: 20150106771Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Inventors: Chia-Cheng Chang, Wei-Kuan Yu, Tsai-Ming Huang, Chin-Min Huang, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Shih-Ming Chang
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Publication number: 20150082265Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Inventors: Chin-Min Huang, Chia-Cheng Chang, Cherng-Shyan Tsay, Chien-Wen Lai, Kong-Beng Thei, Hua-Tai Lin, Hung-Chang Hsieh
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Patent number: 8972912Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.Type: GrantFiled: September 18, 2013Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Min Huang, Chia-Cheng Chang, Cherng-Shyan Tsay, Chien-Wen Lai, Kong-Beng Thei, Hua-Tai Lin, Hung-Chang Hsieh