Abstract: Embodiments herein relate to optimizing the operation of multiple integrated circuits (ICs) operating in parallel. In one aspect, the ICs are arranged in a voltage-stacked configuration, and an operating frequency of each IC is controlled using a tunable replica circuit to stabilize its voltage drop. The tunable replica circuit mimics a critical path on the IC. In another aspect, an IC is divided into top and bottom portions which are in respective voltage domains on a substrate. The substrate include a deep n-well region for the higher voltage domain. In another aspect, a physically unclonable function (PUF) is used to generate identifiers for each IC among a multiple ICs on a board. Entropy sources of the PUF generate bits of the identifiers. Unstable entropy sources are identified and their bits are masked out.

Abstract: A delay-locked loop includes an override controller for controlling the frequency range within which the loop operates. The override controller controls this range based on the output of a detector which compares a phase error between input and output frequency signals to a predetermined range. If the phase error lies outside this range, the controller disables a phase detector to allow the input signal delay to be adjusted based on the output of the range detector. Delay adjustments may be iteratively performed until the range detector determines that the phase error lies within the predetermined range. At this point, the override controller activates the phase detector, and the phase detector is allowed to control further delay adjustments until the phase error is eliminated or reduced, for example, to within tolerable limits.

Abstract: A delay-locked loop includes an override controller for controlling the frequency range within which the loop operates. The override controller controls this range based on the output of a detector which compares a phase error between input and output frequency signals to a predetermined range. If the phase error lies outside this range, the controller disables a phase detector to allow the input signal delay to be adjusted based on the output of the range detector. Delay adjustments may be iteratively performed until the range detector determines that the phase error lies within the predetermined range. At this point, the override controller activates the phase detector, and the phase detector is allowed to control further delay adjustments until the phase error is eliminated or reduced, for example, to within tolerable limits.

Abstract: An adaptive distance calculating neural network classifier chip accepts high dimensionality input pattern vectors with up to 256 5-bit elements per vector and compares the input vector with up to 1024 prototype vectors stored on-chip by calculating the distance between the input vector and each of the prototype vectors. The classifier further provides for identifying up to 64 classes to which the prototype vectors belong. If the distance between input and prototype vector is less than a programmable threshold distance, the prototype fires and the class to which it belongs is identified. If prototype vectors belonging to more than one class fire, a probabilistic model based on Parzen windows may be invoked to resolve the classification by providing the relative probabilities of various class membership. The classifier chip is trainable by supplying appropriate training vectors and associated class membership.

Abstract: An improved method for programming a selected memory cell in a virtual ground EPROM array avoids the disturbance of data stored in adjacent memory cells. To avoid disturbance of adjacent cells during programming, the array is efficiently debiased utilizing intercolumn passgates along with slow ramping of the selected column line voltage. The method avoids the disturbance of data stored in adjacent memory cells by first selecting a row line coupled to the selected memory cell and the memory cells adjacent to it. Next, column lines coupled to the source and drain regions of memory cells on one side of the selected memory cell and column lines coupled to the source and drain regions of memory cells on the other side of the selected memory cell are coupled to first and second nodes respectively. The first node is coupled to ground.

Abstract: A novel associative network architecture is described in which a neural network is subdivided into a plurality of smaller blocks. Each block comprises an array of pattern matching cells which is used for calculating the relative match, or Hamming distance, between an input pattern and a stored weight pattern. The cells are arranged in columns along one or more local summing lines. The total current flowing along the local summing lines for a given block corresponds to the match for that block. Each of the blocks are coupled together using a plurality of global summing lines. The global summing lines sum the individual current contributions from the local summing lines of each associated block. Coupling between the local column lines and the global summing lines is achieved by using a specialized coupling device which permits control of the coupling ratio between the lines.

Abstract: An apparatus and method for improved reading/programming of a virtual ground EPROM array includes a selected memory cell within the array which is accessed so as to avoid parasitic current flow in adjacent cells by first selecting the row line coupled to the control gate electrode of the selected cell. Next, a first column line coupled to the source of the selected cell is grounded. A second column line is coupled to the drain of the selected cell and a third column line is coupled to the drain of the adjacent cell. Simultaneously, a first potential is applied to the second column line to conditionally flow a read current through the selected cell while the second potential is applied to the third column line to shield the adjacent cell from parasitic current. To avoid disturbance of adjacent cells during programming, the array is effectively debiased utilizing intercolumn pass gates along with slow ramping of the selected column voltage.

Abstract: A semiconductor cell for producing an output current that is related to the match between an input vector pattern and a weighting pattern is described. The cell is particularly useful as a synapse cell within a neural network to perform pattern recognition tasks. The cell includes a pair of input lines for receiving a differential input vector element value and a pair of output lines for providing a difference current to a current summing neural amplifier. A plurality of floating gate devices each having a floating gate member are employed in the synapse cell to store charge in accordance with a predetermined weight pattern. Each of the floating gate devices is uniquely coupled to a combination of an output current line and an input voltage line such that the difference current provided to the neural amplifier is related to the match between the input vector and the stored weight.

Abstract: A virtual ground electrically programmable read-only memory device in which disturbance to neighboring cells is practically eliminated, is disclosed. In one embodiment the memory device comprises a plurality of memory cells formed in a semiconductor substrate and arranged in rows and columns so as to form an array. During read operations, pairs of adjacent cells are accessed simultaneously by grounding a single column line within the array. The two adjacent column lines--one on each side of the grounded column line--are coupled to separate read paths. Within the array, rows of cells store bits from a plurality of data bytes according to a pattern in which pairs of adjacent cells store different bits from different bytes.