Patents by Inventor Chin-Shan Hou

Chin-Shan Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6024887
    Abstract: A method for stripping an ion implanted photoresist layer from a substrate. There is first provided a substrate. There is then formed over the substrate an ion implanted photoresist layer. There is then treated the ion implated photoresist layer with a first plasma employing a first etchant gas composition comprising a fluorine containing species to form a fluorine plasma treated ion implanted photoresist layer. Finally, there is then stripped from the substrate the fluorine plasma treated ion implanted photoresist layer with a second plasma employing a second etchant gas composition comprising an oxygen containing species without the fluorine containing species. The ion implanted photoresist layer is stripped from the substrate without plasma induced damage to the substrate.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: February 15, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: So-Wen Kuo, Chin-Shan Hou, Yung Jung Chang
  • Patent number: 5953601
    Abstract: A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: September 14, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ruey-Yun Shiue, Chin-Shan Hou, Yi-Hsun Wu, Lin-June Wu