Patents by Inventor Chin-Shen LIN

Chin-Shen LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118673
    Abstract: Semiconductor devices are provided. A semiconductor device includes a power switch, a first power mesh and a second power mesh. The power switch has a first terminal and a second terminal. The first power mesh is directly connected to the first terminal of the power switch. The second power mesh is directly connected to the second terminal of the power switch. The first power mesh includes a first power rail over the power switch and extending in a first direction. The second power mesh includes a second power rail under the power switch and extending in the first direction. The first and second power rails are separated from each other.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Inventors: Wan-Yu LO, Chin-Shen LIN, Chi-Yu LU, Kuo-Nan YANG, Chih-Liang CHEN, Chung-Hsing WANG
  • Publication number: 20250117564
    Abstract: A method of forming an integrated circuit device includes forming first segments extending in a first direction in a first conductive layer; forming second segments extending in the first direction in the first conductive layer, the forming the first and second segments including: interspersing the first and second segments relative to a second direction perpendicular to the first direction such that: the first segments are symmetrically spaced apart relative to each other, the second segments are symmetrically spaced apart relative to each other, and ones of the second segments are substantially asymmetrically spaced between corresponding adjacent ones of the first segments.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Hiranmay BISWAS, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG
  • Patent number: 12243821
    Abstract: A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin
  • Patent number: 12191248
    Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Hsiang-Ku Shen, Dian-Hau Chen
  • Patent number: 12182488
    Abstract: A device includes a power grid (PG) arrangement including: first and second segments in a first conductive layer which are conductive and extend in a first direction, the first segments being configured for a first reference voltage and the second segments being configured for a second reference voltage; the first and second segments being interspersed relative to a second direction, the second direction being perpendicular to the first direction; and relative to the second direction, the first segments being symmetrically spaced apart relative to each other, the second segments being symmetrically spaced apart relative to each other, and the second segments being substantially asymmetrically spaced between corresponding adjacent ones of the first segments.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang
  • Patent number: 12176288
    Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Wan-Yu Lo, Chin-Shen Lin, Chi-Yu Lu, Kuo-Nan Yang, Chih-Liang Chen, Chung-Hsing Wang
  • Publication number: 20240387354
    Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Hsiang-Ku SHEN, Dian-Hau CHEN
  • Publication number: 20240379552
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
  • Patent number: 12107048
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan, Jhih-Hong Ye
  • Patent number: 12093625
    Abstract: In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lo, Kuo-Nan Yang, Chin-Shen Lin, Chung-Hsing Wang
  • Publication number: 20240258200
    Abstract: A semiconductor devices includes a substrate, a power grid structure, and a through via penetrating the substrate. The power grid structure includes: first and second rails extending along a first direction, a conductive wire, a third rail, a conductive via, and a connecting member. The conductive wire is between the first and second rails, and extends along the first direction. The third rail is below the first rail, the second rail and the conductive wire, and extends along a second direction perpendicular to the first direction. The conductive via is between and electrically couples the conductive wire to the third rail. The connecting member is between and electrically couples the first rail to the conductive wire. The through via extends through the substrate and along a third direction perpendicular to the first direction and the second direction. The through via is disposed on and coupled to the conductive wire.
    Type: Application
    Filed: May 30, 2023
    Publication date: August 1, 2024
    Inventors: Chin-Shen LIN, Ren-Zheng LIAO, Hao-Tien KAN, Yung-Fong LU
  • Publication number: 20240234321
    Abstract: A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.
    Type: Application
    Filed: February 1, 2024
    Publication date: July 11, 2024
    Inventors: Hiranmay BISWAS, Chi-Yeh YU, Kuo-Nan YANG, Chung-Hsing WANG, Stefan RUSU, Chin-Shen LIN
  • Patent number: 11943939
    Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Kai Hsu, Jerry Chang Jui Kao, Chin-Shen Lin, Ming-Tao Yu, Tzu-Ying Lin, Chung-Hsing Wang
  • Patent number: 11935833
    Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Kuo-Nan Yang, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin
  • Patent number: 11929331
    Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20230420369
    Abstract: An integrated circuit (IC) device includes a substrate with a power control circuit, front and back side metal layers, and first and second feed through vias (FTVs). The front side metal layer has first and second front side power rails. The back side metal layer has first and second back side power rails. The first FTV extends through the substrate, and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate, and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first and second front side power rails, and is controllable to electrically connect the first front side power rail to the second front side power rail, or electrically disconnect the first front side power rail from the second front side power rail.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 28, 2023
    Inventors: Chin-Shen LIN, Luk LU, Hao-Tien KAN, Ren-Zheng LIAO
  • Publication number: 20230403868
    Abstract: A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Jerry Chang Jui KAO, Meng-Kai HSU, Chin-Shen LIN, Ming-Tao YU, Tzu-Ying LIN, Chung-Hsing WANG
  • Publication number: 20230401370
    Abstract: A method executed at least partially by a processor includes determining a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the method further includes performing a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The determining the power parameter is performed before a routing operation in the IC layout diagram.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 14, 2023
    Inventors: Chin-Shen LIN, Hiranmay BISWAS, Kuo-Nan YANG, Chung-Hsing WANG
  • Publication number: 20230385518
    Abstract: A method of forming an integrated circuit includes forming at least a first or a second set of devices in a substrate, forming an interconnect structure over the first or second set of devices, and depositing a set of conductive structures on the interconnect structure. The first and second set of devices are configured to operate on a first supply voltage. Forming the interconnect structure includes depositing a set of insulating layers over the first or second set of devices, etching the set of insulating layers thereby forming a set of trenches, depositing a conductive material within the set of trenches, thereby forming a set of metal layers, and forming a portion of a header circuit between a first and a second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 30, 2023
    Inventors: John LIN, Chin-Shen LIN, Kuo-Nan YANG, Chung-Hsing WANG
  • Publication number: 20230376667
    Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Hiranmay BISWAS, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG