Patents by Inventor Chin-Tau Lea
Chin-Tau Lea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10499125Abstract: A scalable AWGR-based optical packet switch, called TASA (short for TDM ASA), is presented in this invention. The switch is a modified version of the ASA switch but does not have its drawbacks. The total port count is N2 and each port can transmit up to N packets of different wavelengths simultaneously. This makes the total capacity of the switch close to (N3×bandwidth of one wavelength channel). But a TASA switch differs from an ASA switch in two major ways. First, a TASA switch does not need an electronic scheduler. This removes a potential bottleneck in the design of an optical packet switch. Second, it can handle any kind of unbalanced loads and can tolerate faults. These qualities, however, are missing in an ASA switch.Type: GrantFiled: December 14, 2016Date of Patent: December 3, 2019Inventor: Chin-Tau Lea
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Patent number: 10033540Abstract: An Internet protocol (IP) based wireless communication network is provided that enables device mobility without handoffs. In an aspect, mobile device of the network is configured to broadcast, via a multicast channel, an anchor router solicitation message comprising a mobile device identifier that identifies the mobile device. The mobile device then receives, via the multicast channel, an assigned IP address from an anchor router device near the mobile device based on detection of the anchor router solicitation message by the anchor router device. The mobile device further employs the assigned IP address to connect with one or more other router devices in response to movement of the mobile device to cell areas of the one or more other router devices of the network.Type: GrantFiled: June 11, 2015Date of Patent: July 24, 2018Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventor: Chin Tau Lea
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Publication number: 20180167702Abstract: A scalable AWGR-based optical packet switch, called TASA (short for TDM ASA), is presented in this invention. The switch is a modified version of the ASA switch but does not have its drawbacks. The total port count is N2 and each port can transmit up to N packets of different wavelengths simultaneously. This makes the total capacity of the switch close to (N3×bandwidth of one wavelength channel). But a TASA switch differs from an ASA switch in two major ways. First, a TASA switch does not need an electronic scheduler. This removes a potential bottleneck in the design of an optical packet switch. Second, it can handle any kind of unbalanced loads and can tolerate faults. These qualities, however, are missing in an ASA switch.Type: ApplicationFiled: December 14, 2016Publication date: June 14, 2018Inventor: Chin-Tau Lea
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Patent number: 9497517Abstract: A scalable AWGR-based optical switching fabric and its scheduling method are presented. The switching fabric consists of three stages: two stages (first and third) of AWGRs interconnected by a second stage of optical space switches. The optical switching system is named ASA for the technologies used to construct the three stages: AWGR, Space switching, and AWGR. The first stage and third stage portions of the switching fabric comprise up to N N×N AWGRs (N inputs and N outputs) and the middle stage N N×N optical space switches, wherein N is an odd integer. This makes the switch's total port count N2. Each port can transmit up to N packets of different wavelengths simultaneously. Thus the total capacity of the switch is around (N3×bandwidth of one wavelength channel).Type: GrantFiled: November 1, 2014Date of Patent: November 15, 2016Inventor: Chin-Tau Lea
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Publication number: 20160127810Abstract: A scalable AWGR-based optical switching fabric and its scheduling method are presented. The switching fabric consists of three stages: two stages (first and third) of AWGRs interconnected by a second stage of optical space switches. The optical switching system is named ASA for the technologies used to construct the three stages: AWGR, Space switching, and AWGR. The first stage and third stage portions of the switching fabric comprise up to N N×N AWGRs (N inputs and N outputs) and the middle stage N N×N optical space switches, wherein N is an odd integer. This makes the switch's total port count N2. Each port can transmit up to N packets of different wavelengths simultaneously. Thus the total capacity of the switch is around (N3×bandwidth of one wavelength channel).Type: ApplicationFiled: November 1, 2014Publication date: May 5, 2016Inventor: Chin-Tau Lea
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Publication number: 20160028554Abstract: An Internet protocol (IP) based wireless communication network is provided that enables device mobility without handoffs. In an aspect, mobile device of the network is configured to broadcast, via a multicast channel, an anchor router solicitation message comprising a mobile device identifier that identifies the mobile device. The mobile device then receives, via the multicast channel, an assigned IP address from an anchor router device near the mobile device based on detection of the anchor router solicitation message by the anchor router device. The mobile device further employs the assigned IP address to connect with one or more other router devices in response to movement of the mobile device to cell areas of the one or more other router devices of the network.Type: ApplicationFiled: June 11, 2015Publication date: January 28, 2016Inventor: Chin Tau Lea
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Patent number: 9166928Abstract: Systems and methods are presented relating to a three stage crossbar based switching system and a scheduling method for transmission of data packets and associated request and grant tokens. The first stage and third stage portions of the switching system contain TDM crossbars, which are interconnected by a middle stage set of crossbars. In an embodiment, the system switching module is a m×m crossbar switch comprising m inputs and m outputs. The switch has a size m2×m2 formed from m×m crossbar modules. Scheduling of data packet servicing is on a frame by frame basis relating to selection based on port addresses and port address groups. Further, time slot interchange is utilized to address time slot mismatch.Type: GrantFiled: September 27, 2012Date of Patent: October 20, 2015Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventor: Chin Tau Lea
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Patent number: 9036482Abstract: Network on Chips (NoC)s with a bufferless and nonblocking architecture are described. Core processors are communicatively coupled together on a substrate with a set of routing nodes based on nonblocking process. A network component routes data packets through the routing nodes and the core processors via communication links. A bufferless cross bar switch facilitates the communication of the data packets and/or path setup packets through the communication links among source processors and destination processors. The communication links include one or more channels, in which a channel comprises a data sub-channel, an acknowledgement sub-channel and a release sub-channel.Type: GrantFiled: December 7, 2012Date of Patent: May 19, 2015Assignee: The Hong Kong University of Science and TechnologyInventor: Chin Tau Lea
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Patent number: 8761125Abstract: Multi-hop architectures of a wireless mesh network (WMN) compatible with the existing WiFi devices and potentially offering a much larger total capacity than a single-hop WiFi cell. The proposed architectures are scalable and do not have the hidden-terminal and the exposed-terminal problems intrinsic in a multi-hop environment that limited the space reuse efficiency of a WMN. The various disclosed architectures also support a fast and efficient location tracking scheme and can overcome the low space reuse efficiency in many of the existing WMN architectures.Type: GrantFiled: May 1, 2007Date of Patent: June 24, 2014Assignee: The Hong Kong University of Science and TechnologyInventor: Chin Tau Lea
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Patent number: 8441926Abstract: This invention presents a new FAC framework that keeps the stateless property of the Internet, allows statistical multiplexing gains, and is capable of handling admission control of both TCP and UDP flows. One of the key inventions of the patent is the solution for the signaling/data path divergence problem inherent in a session layer FAC scheme. The solution consists of two components. First, we keep the paths in the network symmetric (i.e. the forward and the backward path are the same) so that we only need to monitor SETUP packets in new flow detection. Second, we select either a tree or a nonblocking mesh topology for the network. Various topologies for constructing nonblocking networks for the proposed FAC architecture are also disclosed.Type: GrantFiled: November 30, 2007Date of Patent: May 14, 2013Assignee: The Hong Kong University of Science and TechnologyInventor: Chin Tau Lea
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Publication number: 20130083793Abstract: Systems and methods are presented relating to a three stage crossbar based switching system and a scheduling method for transmission of data packets and associated request and grant tokens. The first stage and third stage portions of the switching system contain TDM crossbars, which are interconnected by a middle stage set of crossbars. In an embodiment, the system switching module is a m×m crossbar switch comprising m inputs and m outputs. The switch has a size m2×m2 formed from m×m crossbar modules. Scheduling of data packet servicing is on a frame by frame basis relating to selection based on port addresses and port address groups. Further, time slot interchange is utilized to address time slot mismatch.Type: ApplicationFiled: September 27, 2012Publication date: April 4, 2013Applicant: The Hong Kong University of Science and TechnologyInventor: Chin Tau LEA
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Patent number: 7898957Abstract: A route computation algorithm, a load-balancing scheme inside a router for making a hop-by-hop routing network (such as the Internet) nonblocking are described in this patent. The output of the route computation algorithm includes a set of link weights that determine the paths of the hop-by-hop routing network. The route computation algorithm and the load-balancing scheme also determine the ingress and egress traffic constraints at each edge router such that as long as the traffic entering and leaving the network does not exceed the constraints, none of the internal links will ever have traversing traffic more than its link capacity. The network is thus non-blocking internally. This greatly simplifies flow admission control and allows hard QoS to be supported inside the network.Type: GrantFiled: November 2, 2006Date of Patent: March 1, 2011Assignee: The Hong Kong University of Science and TechnologyInventors: Chin-Tau Lea, Jian Chu
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Patent number: 7656886Abstract: A method and system for computing the maximum amount of admissible ingress and egress traffic of each edge router of the MPLS core network is presented. As long as the ingress and egress traffic amounts are below the admissible amount limit, traffic routes through any link in the network will never exceeds the link capacity. A calculation scheme and a load-distribution scheme make an Internet MPLS backbone network non-blocking. The output of the route computation algorithm includes a set of paths for any source-destination pair and the load distribution ratios among the paths. The routing algorithm and the associated distribution scheme will determine how to balance the loads that meet the distribution requirements specified by the ratios computed from the route algorithm. This greatly simplifies call admission control and allows hard QoS to be supported in a large scale and cross domains in the Internet.Type: GrantFiled: October 3, 2005Date of Patent: February 2, 2010Inventors: Chin-Tau Lea, Jian Chu
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Publication number: 20090141624Abstract: This invention presents a new FAC framework that keeps the stateless property of the Internet, allows statistical multiplexing gains, and is capable of handling admission control of both TCP and UDP flows. One of the key inventions of the patent is the solution for the signaling/data path divergence problem inherent in a session layer FAC scheme. The solution consists of two components. First, we keep the paths in the network symmetric (i.e. the forward and the backward path are the same) so that we only need to monitor SETUP packets in new flow detection. Second, we select either a tree or a nonblocking mesh topology for the network. Various topologies for constructing nonblocking networks for the proposed FAC architecture are also disclosed.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventor: Chin Tau LEA
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Publication number: 20070297371Abstract: Multi-hop architectures of a wireless mesh network (MWN) compatible with the existing WiFi devices and potentially offering a much larger total capacity than a single-hop WiFi cell. The proposed architectures are scalable and do not have the hidden-terminal and the exposed-terminal problems intrinsic in a multi-hop environment that limited the space reuse efficiency of a WMN. The various disclosed architectures also support a fast and efficient location tracking scheme and can overcome the low space reuse efficiency in many of the existing WMN architectures.Type: ApplicationFiled: May 1, 2007Publication date: December 27, 2007Applicant: Hong Kong University of Science and TechnologyInventor: Chin Tau Lea
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Publication number: 20070076615Abstract: A route computation algorithm, a load-balancing scheme inside a router for making a hop-by-hop routing network (such as the Internet) nonblocking are described in this patent. The output of the route computation algorithm includes a set of link weights that determine the paths of the hop-by-hop routing network. The route computation algorithm and the load-balancing scheme also determine the ingress and egress traffic constraints at each edge router such that as long as the traffic entering and leaving the network does not exceed the constraints, none of the internal links will ever have traversing traffic more than its link capacity. The network is thus non-blocking internally. This greatly simplifies flow admission control and allows hard QoS to be supported inside the network.Type: ApplicationFiled: November 2, 2006Publication date: April 5, 2007Inventors: Chin-Tau Lea, Jian Chu
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Publication number: 20060176809Abstract: A method and system for computing the maximum amount of admissible ingress and egress traffic of each edge router of the MPLS core network is presented. As long as the ingress and egress traffic amounts are below the admissible amount limit, traffic routes through any link in the network will never exceeds the link capacity. A calculation scheme and a load-distribution scheme make an Internet MPLS backbone network non-blocking. The output of the route computation algorithm includes a set of paths for any source-destination pair and the load distribution ratios among the paths. The routing algorithm and the associated distribution scheme will determine how to balance the loads that meet the distribution requirements specified by the ratios computed from the route algorithm. This greatly simplifies call admission control and allows hard QoS to be supported in a large scale and cross domains in the Internet.Type: ApplicationFiled: October 3, 2005Publication date: August 10, 2006Inventors: Chin-Tau Lea, Jian Chu
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Patent number: 7046687Abstract: Configurable virtual output queues (VOQs) in a scalable switching system and methods of using the queues are provided. The system takes advantage of the fact that not all VOQs are active or need to exist at one time. Thus, the system advantageously uses configurable VOQs and may not dedicate memory space and logic to all possible VOQs at one time.Type: GrantFiled: January 16, 2002Date of Patent: May 16, 2006Assignee: Tau NetworksInventors: Philip Desborough Pritchard Brown, Peter Johnson, Chin-Tau Lea
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Publication number: 20050289326Abstract: A reduced instruction set pipelined processor having an instruction fetch stage, an instruction decode stage, an executive stage and a write back stage and programmed with a single program which is structured to implement a function performed by a finite state machine. Only read after write data hazards exist in said processor, and these data hazards are eliminated by a forwarding unit in said executive stage which does an address comparison between the executive and write back stages and decides if a data hazard exists in accordance with predetermined logic. If a data hazard exists, suitable control signals are generated to control switching by multiplexers to supply operands to said ALU from said forwarding unit so as to eliminate said data hazards. Pipeline stall control hazards are reduced by inserting useful delay-slot instructions following at least some branch instructions in said program.Type: ApplicationFiled: June 21, 2005Publication date: December 29, 2005Inventor: Chin-Tau Lea
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Patent number: 6920135Abstract: Systems and method for switching packets of information between ports are provided. One system comprises a plurality of port processors, a switch fabric and a scheduler. The port processors send packet headers to the scheduler, which resolves contentions between packet headers with the same destination port addresses. The scheduler sends request-grant information to the port processors. The port processors send packets as specified by the request-grant information to the switch fabric. The switch fabric transfers the packets between the port processors according to the destination port addresses of the packets.Type: GrantFiled: January 23, 2001Date of Patent: July 19, 2005Assignee: Tau NetworksInventor: Chin-Tau Lea