Patents by Inventor Chin-Tau Lea

Chin-Tau Lea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10499125
    Abstract: A scalable AWGR-based optical packet switch, called TASA (short for TDM ASA), is presented in this invention. The switch is a modified version of the ASA switch but does not have its drawbacks. The total port count is N2 and each port can transmit up to N packets of different wavelengths simultaneously. This makes the total capacity of the switch close to (N3×bandwidth of one wavelength channel). But a TASA switch differs from an ASA switch in two major ways. First, a TASA switch does not need an electronic scheduler. This removes a potential bottleneck in the design of an optical packet switch. Second, it can handle any kind of unbalanced loads and can tolerate faults. These qualities, however, are missing in an ASA switch.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 3, 2019
    Inventor: Chin-Tau Lea
  • Patent number: 10033540
    Abstract: An Internet protocol (IP) based wireless communication network is provided that enables device mobility without handoffs. In an aspect, mobile device of the network is configured to broadcast, via a multicast channel, an anchor router solicitation message comprising a mobile device identifier that identifies the mobile device. The mobile device then receives, via the multicast channel, an assigned IP address from an anchor router device near the mobile device based on detection of the anchor router solicitation message by the anchor router device. The mobile device further employs the assigned IP address to connect with one or more other router devices in response to movement of the mobile device to cell areas of the one or more other router devices of the network.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 24, 2018
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Chin Tau Lea
  • Publication number: 20180167702
    Abstract: A scalable AWGR-based optical packet switch, called TASA (short for TDM ASA), is presented in this invention. The switch is a modified version of the ASA switch but does not have its drawbacks. The total port count is N2 and each port can transmit up to N packets of different wavelengths simultaneously. This makes the total capacity of the switch close to (N3×bandwidth of one wavelength channel). But a TASA switch differs from an ASA switch in two major ways. First, a TASA switch does not need an electronic scheduler. This removes a potential bottleneck in the design of an optical packet switch. Second, it can handle any kind of unbalanced loads and can tolerate faults. These qualities, however, are missing in an ASA switch.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventor: Chin-Tau Lea
  • Patent number: 9497517
    Abstract: A scalable AWGR-based optical switching fabric and its scheduling method are presented. The switching fabric consists of three stages: two stages (first and third) of AWGRs interconnected by a second stage of optical space switches. The optical switching system is named ASA for the technologies used to construct the three stages: AWGR, Space switching, and AWGR. The first stage and third stage portions of the switching fabric comprise up to N N×N AWGRs (N inputs and N outputs) and the middle stage N N×N optical space switches, wherein N is an odd integer. This makes the switch's total port count N2. Each port can transmit up to N packets of different wavelengths simultaneously. Thus the total capacity of the switch is around (N3×bandwidth of one wavelength channel).
    Type: Grant
    Filed: November 1, 2014
    Date of Patent: November 15, 2016
    Inventor: Chin-Tau Lea
  • Publication number: 20160127810
    Abstract: A scalable AWGR-based optical switching fabric and its scheduling method are presented. The switching fabric consists of three stages: two stages (first and third) of AWGRs interconnected by a second stage of optical space switches. The optical switching system is named ASA for the technologies used to construct the three stages: AWGR, Space switching, and AWGR. The first stage and third stage portions of the switching fabric comprise up to N N×N AWGRs (N inputs and N outputs) and the middle stage N N×N optical space switches, wherein N is an odd integer. This makes the switch's total port count N2. Each port can transmit up to N packets of different wavelengths simultaneously. Thus the total capacity of the switch is around (N3×bandwidth of one wavelength channel).
    Type: Application
    Filed: November 1, 2014
    Publication date: May 5, 2016
    Inventor: Chin-Tau Lea
  • Publication number: 20160028554
    Abstract: An Internet protocol (IP) based wireless communication network is provided that enables device mobility without handoffs. In an aspect, mobile device of the network is configured to broadcast, via a multicast channel, an anchor router solicitation message comprising a mobile device identifier that identifies the mobile device. The mobile device then receives, via the multicast channel, an assigned IP address from an anchor router device near the mobile device based on detection of the anchor router solicitation message by the anchor router device. The mobile device further employs the assigned IP address to connect with one or more other router devices in response to movement of the mobile device to cell areas of the one or more other router devices of the network.
    Type: Application
    Filed: June 11, 2015
    Publication date: January 28, 2016
    Inventor: Chin Tau Lea
  • Patent number: 9166928
    Abstract: Systems and methods are presented relating to a three stage crossbar based switching system and a scheduling method for transmission of data packets and associated request and grant tokens. The first stage and third stage portions of the switching system contain TDM crossbars, which are interconnected by a middle stage set of crossbars. In an embodiment, the system switching module is a m×m crossbar switch comprising m inputs and m outputs. The switch has a size m2×m2 formed from m×m crossbar modules. Scheduling of data packet servicing is on a frame by frame basis relating to selection based on port addresses and port address groups. Further, time slot interchange is utilized to address time slot mismatch.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 20, 2015
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventor: Chin Tau Lea
  • Patent number: 9036482
    Abstract: Network on Chips (NoC)s with a bufferless and nonblocking architecture are described. Core processors are communicatively coupled together on a substrate with a set of routing nodes based on nonblocking process. A network component routes data packets through the routing nodes and the core processors via communication links. A bufferless cross bar switch facilitates the communication of the data packets and/or path setup packets through the communication links among source processors and destination processors. The communication links include one or more channels, in which a channel comprises a data sub-channel, an acknowledgement sub-channel and a release sub-channel.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 19, 2015
    Assignee: The Hong Kong University of Science and Technology
    Inventor: Chin Tau Lea
  • Patent number: 8761125
    Abstract: Multi-hop architectures of a wireless mesh network (WMN) compatible with the existing WiFi devices and potentially offering a much larger total capacity than a single-hop WiFi cell. The proposed architectures are scalable and do not have the hidden-terminal and the exposed-terminal problems intrinsic in a multi-hop environment that limited the space reuse efficiency of a WMN. The various disclosed architectures also support a fast and efficient location tracking scheme and can overcome the low space reuse efficiency in many of the existing WMN architectures.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: June 24, 2014
    Assignee: The Hong Kong University of Science and Technology
    Inventor: Chin Tau Lea
  • Patent number: 8441926
    Abstract: This invention presents a new FAC framework that keeps the stateless property of the Internet, allows statistical multiplexing gains, and is capable of handling admission control of both TCP and UDP flows. One of the key inventions of the patent is the solution for the signaling/data path divergence problem inherent in a session layer FAC scheme. The solution consists of two components. First, we keep the paths in the network symmetric (i.e. the forward and the backward path are the same) so that we only need to monitor SETUP packets in new flow detection. Second, we select either a tree or a nonblocking mesh topology for the network. Various topologies for constructing nonblocking networks for the proposed FAC architecture are also disclosed.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: May 14, 2013
    Assignee: The Hong Kong University of Science and Technology
    Inventor: Chin Tau Lea
  • Publication number: 20130083793
    Abstract: Systems and methods are presented relating to a three stage crossbar based switching system and a scheduling method for transmission of data packets and associated request and grant tokens. The first stage and third stage portions of the switching system contain TDM crossbars, which are interconnected by a middle stage set of crossbars. In an embodiment, the system switching module is a m×m crossbar switch comprising m inputs and m outputs. The switch has a size m2×m2 formed from m×m crossbar modules. Scheduling of data packet servicing is on a frame by frame basis relating to selection based on port addresses and port address groups. Further, time slot interchange is utilized to address time slot mismatch.
    Type: Application
    Filed: September 27, 2012
    Publication date: April 4, 2013
    Applicant: The Hong Kong University of Science and Technology
    Inventor: Chin Tau LEA
  • Patent number: 7898957
    Abstract: A route computation algorithm, a load-balancing scheme inside a router for making a hop-by-hop routing network (such as the Internet) nonblocking are described in this patent. The output of the route computation algorithm includes a set of link weights that determine the paths of the hop-by-hop routing network. The route computation algorithm and the load-balancing scheme also determine the ingress and egress traffic constraints at each edge router such that as long as the traffic entering and leaving the network does not exceed the constraints, none of the internal links will ever have traversing traffic more than its link capacity. The network is thus non-blocking internally. This greatly simplifies flow admission control and allows hard QoS to be supported inside the network.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: March 1, 2011
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Chin-Tau Lea, Jian Chu
  • Patent number: 7656886
    Abstract: A method and system for computing the maximum amount of admissible ingress and egress traffic of each edge router of the MPLS core network is presented. As long as the ingress and egress traffic amounts are below the admissible amount limit, traffic routes through any link in the network will never exceeds the link capacity. A calculation scheme and a load-distribution scheme make an Internet MPLS backbone network non-blocking. The output of the route computation algorithm includes a set of paths for any source-destination pair and the load distribution ratios among the paths. The routing algorithm and the associated distribution scheme will determine how to balance the loads that meet the distribution requirements specified by the ratios computed from the route algorithm. This greatly simplifies call admission control and allows hard QoS to be supported in a large scale and cross domains in the Internet.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: February 2, 2010
    Inventors: Chin-Tau Lea, Jian Chu
  • Publication number: 20090141624
    Abstract: This invention presents a new FAC framework that keeps the stateless property of the Internet, allows statistical multiplexing gains, and is capable of handling admission control of both TCP and UDP flows. One of the key inventions of the patent is the solution for the signaling/data path divergence problem inherent in a session layer FAC scheme. The solution consists of two components. First, we keep the paths in the network symmetric (i.e. the forward and the backward path are the same) so that we only need to monitor SETUP packets in new flow detection. Second, we select either a tree or a nonblocking mesh topology for the network. Various topologies for constructing nonblocking networks for the proposed FAC architecture are also disclosed.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Inventor: Chin Tau LEA
  • Publication number: 20070297371
    Abstract: Multi-hop architectures of a wireless mesh network (MWN) compatible with the existing WiFi devices and potentially offering a much larger total capacity than a single-hop WiFi cell. The proposed architectures are scalable and do not have the hidden-terminal and the exposed-terminal problems intrinsic in a multi-hop environment that limited the space reuse efficiency of a WMN. The various disclosed architectures also support a fast and efficient location tracking scheme and can overcome the low space reuse efficiency in many of the existing WMN architectures.
    Type: Application
    Filed: May 1, 2007
    Publication date: December 27, 2007
    Applicant: Hong Kong University of Science and Technology
    Inventor: Chin Tau Lea
  • Publication number: 20070076615
    Abstract: A route computation algorithm, a load-balancing scheme inside a router for making a hop-by-hop routing network (such as the Internet) nonblocking are described in this patent. The output of the route computation algorithm includes a set of link weights that determine the paths of the hop-by-hop routing network. The route computation algorithm and the load-balancing scheme also determine the ingress and egress traffic constraints at each edge router such that as long as the traffic entering and leaving the network does not exceed the constraints, none of the internal links will ever have traversing traffic more than its link capacity. The network is thus non-blocking internally. This greatly simplifies flow admission control and allows hard QoS to be supported inside the network.
    Type: Application
    Filed: November 2, 2006
    Publication date: April 5, 2007
    Inventors: Chin-Tau Lea, Jian Chu
  • Publication number: 20060176809
    Abstract: A method and system for computing the maximum amount of admissible ingress and egress traffic of each edge router of the MPLS core network is presented. As long as the ingress and egress traffic amounts are below the admissible amount limit, traffic routes through any link in the network will never exceeds the link capacity. A calculation scheme and a load-distribution scheme make an Internet MPLS backbone network non-blocking. The output of the route computation algorithm includes a set of paths for any source-destination pair and the load distribution ratios among the paths. The routing algorithm and the associated distribution scheme will determine how to balance the loads that meet the distribution requirements specified by the ratios computed from the route algorithm. This greatly simplifies call admission control and allows hard QoS to be supported in a large scale and cross domains in the Internet.
    Type: Application
    Filed: October 3, 2005
    Publication date: August 10, 2006
    Inventors: Chin-Tau Lea, Jian Chu
  • Patent number: 7046687
    Abstract: Configurable virtual output queues (VOQs) in a scalable switching system and methods of using the queues are provided. The system takes advantage of the fact that not all VOQs are active or need to exist at one time. Thus, the system advantageously uses configurable VOQs and may not dedicate memory space and logic to all possible VOQs at one time.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: May 16, 2006
    Assignee: Tau Networks
    Inventors: Philip Desborough Pritchard Brown, Peter Johnson, Chin-Tau Lea
  • Publication number: 20050289326
    Abstract: A reduced instruction set pipelined processor having an instruction fetch stage, an instruction decode stage, an executive stage and a write back stage and programmed with a single program which is structured to implement a function performed by a finite state machine. Only read after write data hazards exist in said processor, and these data hazards are eliminated by a forwarding unit in said executive stage which does an address comparison between the executive and write back stages and decides if a data hazard exists in accordance with predetermined logic. If a data hazard exists, suitable control signals are generated to control switching by multiplexers to supply operands to said ALU from said forwarding unit so as to eliminate said data hazards. Pipeline stall control hazards are reduced by inserting useful delay-slot instructions following at least some branch instructions in said program.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 29, 2005
    Inventor: Chin-Tau Lea
  • Patent number: 6920135
    Abstract: Systems and method for switching packets of information between ports are provided. One system comprises a plurality of port processors, a switch fabric and a scheduler. The port processors send packet headers to the scheduler, which resolves contentions between packet headers with the same destination port addresses. The scheduler sends request-grant information to the port processors. The port processors send packets as specified by the request-grant information to the switch fabric. The switch fabric transfers the packets between the port processors according to the destination port addresses of the packets.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: July 19, 2005
    Assignee: Tau Networks
    Inventor: Chin-Tau Lea