Patents by Inventor Chin Teck Siong

Chin Teck Siong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014123
    Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Kuan-Hsiang Mao, Chin Teck Siong, Pey Fang Hiew, Wen Yuan Chuang, Sharon Huey Lin Tay, Wen Hung Huang
  • Publication number: 20230369168
    Abstract: An integrated circuit (IC) package includes one or more microelectronic devices disposed between a first side and an opposing second side of the IC package and further includes a metal frame structure comprising a metal layer disposed at the second side, an embedded ground plane (EGP) structure encircling the one or more microelectronic devices, and a set of stacked conductive structures extending from the EGP structure to the first side through a set of one or more redistribution layers at the first side. The IC package further can include an array of package contacts disposed at the first side and an encapsulant layer encapsulating the one or more microelectronic devices in a volume defined by an inner sidewall of the EGP structure.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Kuan-Hsiang Mao, Chin Teck Siong, Wen Hung Huang
  • Publication number: 20230343749
    Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Applicant: NXP B.V.
    Inventors: Kuan-Hsiang Mao, Norazham Mohd Sukemi, Chin Teck Siong, Tsung Nan Lo, Wen Hung Huang
  • Patent number: 11056457
    Abstract: A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 6, 2021
    Assignee: NXP USA, INC.
    Inventors: Boon Yew Low, Lan Chu Tan, Wai Yew Lo, Poh Leng Eu, Chin Teck Siong
  • Publication number: 20200105709
    Abstract: A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Boon Yew Low, Lan Chu Tan, Wai Yew Lo, Poh Leng Eu, Chin Teck Siong
  • Patent number: 10325826
    Abstract: A substrate having a die attach area for receiving a semiconductor die includes a recessed area for receiving die attach adhesive. The recessed area prevents die attach adhesive from bleeding into the surrounding area and onto substrate connection sites, where it could compromise a wire bond formed on such a connection site. The recessed area has a zig-zag pattern, which allows for sufficient amounts of adhesive to be used to securely attach the die to the substrate, yet does not enlarge the recessed area such that the package size may be adversely affected.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 18, 2019
    Assignee: NXP USA, INC.
    Inventors: Ly Hoon Khoo, Chin Teck Siong, Vanessa Wyn Jean Tan
  • Patent number: 9287236
    Abstract: A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: March 15, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Teck Beng Lau, Chee Seng Foong, Chin Teck Siong
  • Patent number: 9257403
    Abstract: An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: February 9, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tu-Anh N. Tran, John G. Arthur, Yin Kheng Au, Chu-Chung Lee, Chin Teck Siong, Meijiang Song, Jia Lin Yap, Matthew J. Zapico
  • Publication number: 20160020189
    Abstract: A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Teck Beng Lau, Chee Seng Foong, Chin Teck Siong
  • Patent number: 9165904
    Abstract: A method of attaching a bond wire to first and second electrical contact pads includes holding the bond wire in a capillary, wherein a first end of the bond wire extends out of an opening in the capillary, attaching the first end of the bond wire to the first electrical contact pad using a ball bonding technique, moving a second end of the bond wire toward the second electrical contact pad after the attachment of the first end of the bond wire, performing an electric flame off on the second end of the bond wire without forming a free air ball, and attaching the second end of the bond wire to the second electrical contact pad after the EFO on the second end of the bond wire.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: October 20, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chin Teck Siong, Zi Song Poh, Lan Chu Tan
  • Publication number: 20150145148
    Abstract: An integrated circuit copper wire bond connection is provided having a copper ball (32) bonded directly to an aluminum bond pad (31) formed on a low-k dielectric layer (30) to form a bond interface structure for the copper ball characterized by a first plurality of geometric features to provide thermal cycling reliability, including an aluminum minima feature (Z1, Z2) located at an outer peripheral location (42) under the copper ball to prevent formation and/or propagation of cracks in the aluminum bond pad.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tu-Anh N. Tran, John G. Arthur, Yin Kheng Au, Chu-Chung Lee, Chin Teck Siong, Meijiang Song, Jia Lin Yap, Matthew J. Zapico
  • Patent number: 8809078
    Abstract: A self-powered circuit package includes a substrate and an integrated circuit (IC). The IC is mounted on a surface of the substrate. An electrical interconnector electrically couples the IC to the substrate. A solar cell is provided having opposing first and second main surfaces. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power. The solar cell is disposed above the IC and electrically connected to the IC by way of the substrate to supply the generated power to the IC. A clear mold compound encapsulates a surface of the substrate, the IC, the electrical interconnector, and the solar cell.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: August 19, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Teck Beng Lau, Wai Yew Lo, Boon Yew Low, Chin Teck Siong
  • Publication number: 20140225211
    Abstract: A self-powered circuit package includes a substrate and an integrated circuit (IC). The IC is mounted on a surface of the substrate. An electrical interconnector electrically couples the IC to the substrate. A solar cell is provided having opposing first and second main surfaces. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power. The solar cell is disposed above the IC and electrically connected to the IC by way of the substrate to supply the generated power to the IC. A clear mold compound encapsulates a surface of the substrate, the IC, the electrical interconnector, and the solar cell.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 14, 2014
    Inventors: Teck Beng Lau, Wai Yew Lo, Boon Yew Low, Chin Teck Siong
  • Patent number: 8778704
    Abstract: A self-powered integrated circuit (IC) device includes a lead frame and a solar cell having first and second main surfaces. The solar cell is mounted on a surface of the lead frame. An IC chip is also provided. A first electrical interconnector electrically couples the IC chip to the lead frame and a second electrical interconnector electrically couples the solar cell to the IC chip. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power that is supplied to the IC chip. A mold compound encapsulates the IC chip, the first and second electrical interconnectors, and at least a portion of the solar cell.
    Type: Grant
    Filed: March 24, 2013
    Date of Patent: July 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Teck Beng Lau, Wai Yew Lo, Chin Teck Siong
  • Publication number: 20130319726
    Abstract: A wire that can be used in a wire bonding step in the assembly of a semiconductor device has a first conductive core, a second conductive core surrounding the first conductive core, and a third conductive core surrounding the first second conductive core. The first and third conductive cores are formed of a material such as Palladium and the second conductive core is formed of a material such as Copper. When the wire is bonded to a bonding pad of a semiconductor die, the first and third conductive cores melt over the free air ball (FAB)surface for the purpose of inhibiting intermetallic corrosion of the bonded ball.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Chin Teck Siong, Lai Cheng Law, Seok Khoon Lee