Abstract: An organic luminescent material includes a host luminescent material and a guest luminescent material.

Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.

Abstract: A WBGA semiconductor package primarily comprises a substrate, a chip, a chip-bonding adhesive, a plurality of bonding wires electrically connecting the chip and the substrate, an encapsulant to encapsulate the chip and the bonding wires, and a plurality of external terminals disposed under the substrate. The substrate has a depression for accommodating the chip-bonding adhesive and a slot for passing through bonding wires. The chip is partially embedded in the depression to dispose on the substrate. During the chip bonding step, the chip-bonding adhesive is confined in the depression in a manner to fill the gaps between the sides of the first chip and the inwalls around the depression to generate a non-planar adhering interface by partially covering the sides of the first chip. Therefore, the total package thickness is reduced, the delamination of the passivation layer and the fractures at the sides of the chip are avoided.

Abstract: A WBGA semiconductor package primarily comprises a substrate, a chip, a chip-bonding adhesive, a plurality of bonding wires electrically connecting the chip and the substrate, an encapsulant to encapsulate the chip and the bonding wires, and a plurality of external terminals disposed under the substrate. The substrate has a depression for accommodating the chip-bonding adhesive and a slot for passing through bonding wires. The chip is partially embedded in the depression to dispose on the substrate. During the chip bonding step, the chip-bonding adhesive is confined in the depression in a manner to fill the gaps between the sides of the first chip and the inwalls around the depression to generate a non-planar adhering interface by partially covering the sides of the first chip. Therefore, the total package thickness is reduced, the delamination of the passivation layer and the fractures at the sides of the chip are avoided.

Abstract: The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted.

Abstract: The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements.

Abstract: A chip mounting device includes at least one chip mounting unit and at least one side rail configured beside the chip mounting unit. The chip mounting unit includes a die pad and a plurality of conductive contacts. The side rail includes at least one identifying element. A chip package array with the above-mentioned chip mounting device is also disclosed. The chip mounting device and chip package array includes the identifying element configured on the side rail to improve the identification of semi-finished packaged chips during chip package process to be read automatically by machines instead of operators, and further decrease the loss caused by misjudgments of operators.

Abstract: A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads and is formed a plurality of contact faces with height differences, a second protrusion portion is protruded from each of the second inner leads. Therefore, the wires connected to the stacked chips, the first protrusion portion of the first inner leads, and the second protrusion portion of the second inner leads can be shorten. And, the wire sweep and short-circuit can be prevented during molding process. In addition, the present invention also discloses a leadframe and manufacturing method for the leadframe and its semiconductor packaging structure.

Abstract: A semiconductor package structure includes a carrier having a plurality of leads, wherein each of the leads is composed of an inner lead and an outer lead; a chip arranged on the bottom surface of the inner leads; an electrical connecting structure and a molding component. The invention discloses that the inner leads are bent outwardly from the horizontal at top surface of the chip to form a ladder-like difference and the outer leads are extended outwardly horizontally, thus a height difference formed between the chip and the outer lead prevents the particles from contacting the chip and the outer lead at the same time to enhance the electrical reliability of the chip.

Abstract: A Chip-On-Lead (COL) semiconductor package is revealed, primarily comprising a plurality of leadframe's leads each having a carrying bar, a finger and a connecting portion connecting the carrying bar to the finger. A chip has a back surface attached to the carrying bars and is electrically connected to the fingers by a plurality of bonding wires. Therein, at least one of the bonding wires overpasses one of the connecting portions without electrical relationship. An insulation tape is attached onto the connecting portions in a manner to be formed between the overpassing section of the bonding wire and the overpast connecting portion so that electrical short can be avoided during wire-bonding processes of the COL semiconductor package. Therefore, the carrying bars under the chip have more flexibility in the layout design of COL semiconductor packages to use die pad(s) with smaller dimensions or even eliminate die pad.

Abstract: A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code.

Abstract: A semiconductor package primarily comprises a plurality of leadframe's leads, a chip, a paddle, an adhesive and an encapsulant encapsulating the components mentioned above. The paddle has a carrying surface and an exposed external surface. The first chip is attached to one surface of the leads. The paddle is attached to an opposing surface of the leads by the adhesive bonding the carrying surface to the leads. Furthermore, the adhesive further encapsulates the gaps between the leads without contaminating the exposed external surface and with the exposed external surface exposed from the encapsulant. Therefore, the leads obtain a better support so that the encapsulated portions of the leads will not shift nor expose from the encapsulant during molding processes without encapsulated bubbles between the leads and the paddle. The heat dissipation is also enhanced.

Abstract: A method of forming an identification code for wire bonders is revealed. Firstly, a chip with a plurality of bonding pads is provided and is disposed on a chip carrier with a plurality of bonding fingers. A binary-code baseline is defined on the chip carrier to divide each of the bonding fingers into a first coding area adjacent the bonding pads and a second coding area far away from the bonding pads. Then, a plurality of bonding wires are formed by wire bonding to electrically connect the bonding pads to the bonding fingers and an ID code for wire bonders is formed at the same time where each bonding wire has an end selectively bonded to either the first coding area or the second coding area of the corresponding bonding finger to form an ID code for wire bonders. Since the ID code for wire bonders is constituted by the selected locations of the ends of the bonding wires, the ID code do not get lost or damaged during packaging processes nor contaminate the packages.

Abstract: Disclosed is a method for assembling a semiconductor device, especially to dispose a plurality of chips on double sides of a chip carrier, such as a lead frame. At least a first chip is disposed on one surface of the chip carrier. Then, a protecting spacer is disposed on the active surface of the first chip. Then, the chip carrier is flipped over and placed on a hot plate where the protecting spacer keeps the active surface of the first chip away from direct contact with the hot plate. After the flipping and placing step, at least a second chip is disposed on another surface of the chip carrier and then is electrically connected to the chip carrier by a plurality of bonding wires. Therefore, any damages to the active surface of the first chip are avoided during disposition and electrical connections of the second chip.

Abstract: A package on package structure includes a first chip package, a second chip package and a conductive film. The first chip package has a portion of first conductive lead which is exposed to the encapsulation body of the first chip package. The conductive film is arranged between the first chip package and the second chip package to adhere to them and electrically connect the first conductive lead and the second chip package. The above-mentioned package on package structure can improve short-circuit phenomenon between leads.

Abstract: A chip package structure and a fabrication method thereof are disclosed herein. The fabrication method includes: providing a substrate, wherein at least a through hole penetrates through the substrate; forming a block element surrounding the through hole of the substrate; forming an adhesive element surrounding the block element; disposing a chip on the substrate to cover the through hole, wherein the chip is fixed on the substrate with the adhesive element, wherein an active surface of the chip faces toward to the through hole and a portion of the active surface exposes to the through hole; electrically connecting the active surface of the chip to the lower surface of the substrate with a electrically-connecting element; and forming an encapsulant covering the abovementioned elements.

Abstract: The tetraphenylsilane-carbazole compound of this invention has the following general formula: wherein R1 and R2 are H, halogen or carbazole having the formula of with at least one of R1 and R2 being carbazole; n=1, 2, 3 or 4; and wherein Si and N substituents are in meta positions on the benzene ring; or wherein R3, R4, R5 and R6 are H, halogen or tetraphenylsilane having the formula of with at least one of R3, R4, R5 and R6 being tetraphenylsilane; and wherein Si and N substituents are in meta positions on the benzene ring. The invented tetraphenylsilane-carbazole compounds are prepared by mixing selected tetraphenylsilane with carbazole in the existence of additives and reacting them under heated conditions, or by mixing selected carbazole with butyl metallic and reacting them under relatively lower temperature. The products may be used as host material for dopants for organic light emitting diode (OLED).

Abstract: This invention relates to tetraphenylmethane-based oxadiazole molecules that act as electron transporting materials to be used in electroluminescent devices. The oxadiazole compounds are of the following formula. Each variable is defined in the specification.

Abstract: This invention relates to a method of preparing a compound of formula (I): The method includes reacting one or more compounds of formula (II): in the presence of a base and a halogenating agent. In formulas (I) and (II) above, each A, independently, is aryl or heteroaryl; each n, independently, is 0–3; and each R1, independently, is C1–C10 alkyl, C3–C20 cycloalkyl, C3–C20 heterocycloalkyl, aryl, heteroaryl, halo, cyano, nitro, ORa, NRaRb, SiRaRbRc, COORa, OC(O)Ra, C(O)NRaRb, N(Ra)—C(O)Rb, or SO3Ra; wherein each of Ra, Rb, and Rc, independently, is H, C1–C10 alkyl, C3–C20 cycloalkyl, C3–C20 heterocycloalkyl, aryl, or heteroaryl; thereby producing the compound of formula (I) in a one-pot reaction. This invention also relates to the compounds prepared by the method described above.

Abstract: This invention relates to a method of preparing a compound of formula (I): The method includes reacting one or more compounds of formula (II): in the presence of a base and a halogenating agent. In formulas (I) and (II) above, each A, independently, is aryl or heteroaryl; each n, independently, is 0-3; and each R1, independently, is C1-C10 alkyl, C3-C20 cycloalkyl, C3-C20 heterocycloalkyl, aryl, heteroaryl, halo, cyano, nitro, ORa, NRaRb, SiRaRbRc, COORa, OC(O)Ra, C(O)NRaRb, N(Ra)—C(O)Rb, or SO3Ra; wherein each of Ra, Rb, and Rc, independently, is H, C1-C10 alkyl, C3-C20 cycloalkyl, C3-C20 heterocycloalkyl, aryl, or heteroaryl; thereby producing the compound of formula (I) in a one-pot reaction. This invention also relates to the compounds prepared by the method described above.