Abstract: Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.

Abstract: An event reporting method, a security management circuit, and a management system are provided. The management system includes first, second, and third security management circuits. The first security management circuit and the second security management are respectively located at a first layer and a second layer of a hierarchy structure. The third security management circuit is located at another layer of the hierarchy structure different from the first layer and the second layer. The first, second, and third security management circuits are respectively configured to determine an event occurring on a host connected to these security management circuits. A dedicated line is communicatively connected between the first and third security management circuits. According to a type of the event determined by the third security management circuit, the third security management circuit reports the event through the dedicated line. Accordingly, a reporting efficiency and system security are improved.

Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.

Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.

Abstract: A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.

Abstract: An electronic device and data transmission protection device thereof are provided. The data transmission protection device includes an input clock signal detector and a control signal generator. The input clock signal detector receives a reference clock signal, and detects a frequency of an input clock signal provided by a host end according to the reference clock signal, and frequencies of the reference clock signal and the input clock signal are different. The control signal generator enables a generated control signal when the frequency of the input clock signal is larger than a safety setting value. The control signal is used to disable the host end to perform a data accessing operation on a protected circuit.

Abstract: The present invention discloses a method and a system of wafer protection of a chemical mechanical process. It takes an image on the polishing pad, and analyzes and identifies the image. If the wafer is out of a polishing head, a signal will be sent to the chemical mechanical polishing station to respond adequately. Otherwise, repeats the image obtaining and its following analysis and identification. The present invention can avoid broken wafers and reduce the station recovery time. Hence, it can increase the up time and the throughput of the station.

Abstract: The present invention discloses a method and a system of wafer protection of a chemical mechanical process. It takes an image on the polishing pad, and analyzes and identifies the image. If the wafer is out of a polishing head, a signal will be sent to the chemical mechanical polishing station to respond adequately. Otherwise, repeats the image obtaining and its following analysis and identification. The present invention can avoid broken wafers and reduce the station recovery time. Hence, it can increase the up time and the throughput of the station.