Patents by Inventor Chin-Tsai Yao
Chin-Tsai Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973014Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.Type: GrantFiled: November 21, 2019Date of Patent: April 30, 2024Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
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Patent number: 10679932Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.Type: GrantFiled: April 27, 2017Date of Patent: June 9, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Ho-Yi Tsai, Chin-Tsai Yao
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Publication number: 20200091059Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.Type: ApplicationFiled: November 21, 2019Publication date: March 19, 2020Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
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Patent number: 10522453Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.Type: GrantFiled: November 16, 2016Date of Patent: December 31, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
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Patent number: 10510720Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.Type: GrantFiled: December 8, 2016Date of Patent: December 17, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Kuo-Hua Yu, Fu-Tang Huang
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Publication number: 20180130774Abstract: A package stack structure is provided, including a first substrate, a second substrate stacked on the first substrate, and an encapsulant formed between the first substrate and the second substrate. A through hole is formed to penetrate the second substrate and allow the encapsulant to be filled therein, thereby increasing the contact area and hence strengthening the bonding between the encapsulant and the second substrate.Type: ApplicationFiled: February 16, 2017Publication date: May 10, 2018Inventors: Chang-Fu Lin, Chin-Tsai Yao, Kuo-Hua Yu, Fu-Tang Huang
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Publication number: 20180061810Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.Type: ApplicationFiled: December 8, 2016Publication date: March 1, 2018Inventors: Chang-Fu Lin, Chin-Tsai Yao, Kuo-Hua Yu, Fu-Tang Huang
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Patent number: 9900996Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.Type: GrantFiled: August 7, 2014Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Ko-Cheng Liu, Fu-Tang Huang
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Patent number: 9842771Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.Type: GrantFiled: May 8, 2014Date of Patent: December 12, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Hung-Ming Chang, Ming-Chin Chuang, Fu-Tang Huang
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Publication number: 20170294371Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.Type: ApplicationFiled: April 27, 2017Publication date: October 12, 2017Inventors: Chang-Fu Lin, Ho-Yi Tsai, Chin-Tsai Yao
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Publication number: 20170207161Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.Type: ApplicationFiled: November 16, 2016Publication date: July 20, 2017Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chun-Tang Lin, Fu-Tang Huang
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Patent number: 9666453Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.Type: GrantFiled: July 11, 2012Date of Patent: May 30, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Ho-Yi Tsai, Chin-Tsai Yao
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Publication number: 20170148679Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Inventors: Chang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Keng-Hung Liu, Fu-Tang Huang
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Patent number: 9607963Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.Type: GrantFiled: April 22, 2014Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Fu-Tang Huang
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Patent number: 9520351Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.Type: GrantFiled: December 9, 2014Date of Patent: December 13, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Ko-Cheng Liu, Fu-Tang Huang
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Patent number: 9425152Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.Type: GrantFiled: February 13, 2015Date of Patent: August 23, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chin-Tsai Yao, Chien-Ping Huang, Chun-Chi Ke
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Patent number: 9368467Abstract: A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost.Type: GrantFiled: October 18, 2012Date of Patent: June 14, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chang-Fu Lin, Ho-Yi Tsai, Chin-Tsai Yao
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Publication number: 20160099204Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.Type: ApplicationFiled: May 12, 2015Publication date: April 7, 2016Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chia-Cheng Chen, Chih-Jen Yang, Fu-Tang Huang
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Publication number: 20150332998Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.Type: ApplicationFiled: December 9, 2014Publication date: November 19, 2015Inventors: Chang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Ko-Cheng Liu, Fu-Tang Huang
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Patent number: 9190387Abstract: A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.Type: GrantFiled: April 15, 2014Date of Patent: November 17, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chin-Tsai Yao, Chien-Ping Huang, Chun-Chi Ke