Patents by Inventor Chin-Tsan Yeh
Chin-Tsan Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170076976Abstract: An isolation structure and a method of fabricating the same are provided. The isolation structure includes a buffer layer and an encapsulation layer. The buffer layer is located in a trench of a substrate. The encapsulation layer is located in the trench and encapsulates around the buffer layer, wherein the buffer layer is unexposed and is not in contacted with the trench. A material of the buffer layer is different from a material of the encapsulation layer.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Chin-Tsan Yeh, Tuung Luoh, Ta-Hung Yang, Kuang-Chao Chen
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Patent number: 9455404Abstract: A memory device is provided. A first conductive layer, a first diffusion barrier layer, a phase change layer, a second diffusion barrier layer and a second conductive layer are disposed on a first electrode layer in sequence to form a stacking structure. A dielectric layer is disposed on the first electrode layer and covers a sidewall of the stacking structure and part of a top surface of the second conductive layer. A second electrode layer is disposed on the dielectric layer and the second conductive layer. Barrier enhancing components are provided between a bottom surface of the first diffusion barrier layer and a top surface of the second diffusion barrier layer. Further, a method of manufacturing a memory device is provided.Type: GrantFiled: January 6, 2015Date of Patent: September 27, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Bing-Lung Yu, Chin-Tsan Yeh
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Publication number: 20160197272Abstract: A memory device is provided. A first conductive layer, a first diffusion barrier layer, a phase change layer, a second diffusion barrier layer and a second conductive layer are disposed on a first electrode layer in sequence to form a stacking structure. A dielectric layer is disposed on the first electrode layer and covers a sidewall of the stacking structure and part of a top surface of the second conductive layer. A second electrode layer is disposed on the dielectric layer and the second conductive layer. Barrier enhancing components are provided between a bottom surface of the first diffusion barrier layer and a top surface of the second diffusion barrier layer. Further, a method of manufacturing a memory device is provided.Type: ApplicationFiled: January 6, 2015Publication date: July 7, 2016Inventors: Bing-Lung Yu, Chin-Tsan Yeh
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Patent number: 9252102Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.Type: GrantFiled: June 6, 2014Date of Patent: February 2, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Bing-Lung Yu, Chin-Tsan Yeh, Yung-Tai Hung, Chin-Ta Su
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Publication number: 20150357286Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Inventors: Bing-Lung Yu, Chin-Tsan Yeh, Yung-Tai Hung, Chin-Ta Su
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Patent number: 8653592Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.Type: GrantFiled: November 8, 2011Date of Patent: February 18, 2014Assignee: Macronix International Co., Ltd.Inventors: Ming-Da Cheng, Chin-Tsan Yeh, Tuung Luoh, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen
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Publication number: 20130241075Abstract: Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Tsan Yeh, Chun-Fu Chen, Yung-Tai Hung, Chin-Ta Su
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Patent number: 8445982Abstract: A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.Type: GrantFiled: June 9, 2011Date of Patent: May 21, 2013Assignee: Macronix International Co., Ltd.Inventors: Chin-Tsan Yeh, Chun-Fu Chen, Yung-Tai Hung, Chin-Ta Su
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Publication number: 20120313214Abstract: A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.Type: ApplicationFiled: June 9, 2011Publication date: December 13, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Tsan Yeh, Chun-Fu Chen, Yung-Tai Hung, Chin-Ta Su
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Patent number: 8288280Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.Type: GrantFiled: July 19, 2007Date of Patent: October 16, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Yung-Tai Hung, Chin-Tsan Yeh, Chin-Ta Su, Ling-Wu Yang, Tung-Han Chuang
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Publication number: 20120049269Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.Type: ApplicationFiled: November 8, 2011Publication date: March 1, 2012Applicant: Macronix International Co., Ltd.Inventors: Ming-Da Cheng, Chin-Tsan Yeh, Tuung Luoh, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen
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Patent number: 8067292Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.Type: GrantFiled: December 24, 2008Date of Patent: November 29, 2011Assignee: Macronix International Co., Ltd.Inventors: Ming-Da Cheng, Chin-Tsan Yeh, Tuung Luoh, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen
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Patent number: 7763517Abstract: A method of forming a non-volatile memory cell is provided. The method comprises: (a) providing a substrate; (b) forming a stacking structure on the substrate, the stacking structure at least comprising an oxide-nitride-oxide layer (ONO layer) and a polysilicon layer thereon; (c) patterning the stacking structure to form a plurality of separated stacking units, each two stacking units having an aperture therebetween; (d) forming a source region and a drain region buried in the substrate at two sides of the each stacking unit; (e) forming an oxide layer in the aperture and over the stacking units; and (f) performing a chemical mechanical polishing (CMP) process to remove the oxide layer over the stacking units and outside the aperture.Type: GrantFiled: February 12, 2007Date of Patent: July 27, 2010Assignee: Macronix International Co., Ltd.Inventors: Chin-Tsan Yeh, Chih-Hsien Lo, Chin-Ta Su, Kuang-Chao Chen
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Publication number: 20090184343Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.Type: ApplicationFiled: December 24, 2008Publication date: July 23, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Da Cheng, Chin-Tsan Yeh, Tuung Luoh, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen
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Publication number: 20090023289Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.Type: ApplicationFiled: July 19, 2007Publication date: January 22, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yung-Tai Hung, Chin-Tsan Yeh, Chin-Ta Su, Ling-Wu Yang, Tung-Han Chuang
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Publication number: 20080194071Abstract: A method of forming a non-volatile memory cell is provided. The method comprises: (a) providing a substrate; (b) forming a stacking structure on the substrate, the stacking structure at least comprising an oxide-nitride-oxide layer (ONO layer) and a polysilicon layer thereon; (c) patterning the stacking structure to form a plurality of separated stacking units, each two stacking units having an aperture therebetween; (d) forming a source region and a drain region buried in the substrate at two sides of the each stacking unit; (e) forming an oxide layer in the aperture and over the stacking units; and (f) performing a chemical mechanical polishing (CMP) process to remove the oxide layer over the stacking units and outside the aperture.Type: ApplicationFiled: February 12, 2007Publication date: August 14, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chin-Tsan Yeh, Chih-Hsien Lo, Chin-Ta Su, Kuang-Chao Chen