Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A semiconductor device may include a compound substrate and a 3-dimensional inductor structure. The compound substrate may include a front surface and a back surface. The 3-dimensional inductor structure may include a front conductive stack, a back conductive layer, and at least one through-hole structure. At least one portion of the front conductive stack may include a first conductive layer disposed on the front surface of the compound substrate, and a second conductive layer disposed on the first conductive layer. The second conductive layer has a thickness ranging between 30 micrometers and 400 micrometers. The back conductive layer is disposed on the back surface of the compound substrate. The at least one through-hole structure penetrates through the compound substrate, and electrically connects the front conductive stack to the back conductive layer.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

Abstract: The art for the design of a class of modified catalysts, the process for preparing such modified catalysts and implementation of such modified catalysts in phosphoric acid fuel cells is disclosed. The modified catalyst comprises a particle of a metal-doped porous material and an amount of a phosphate-containing acid group or phosphate-containing acid groups. The particle of the metal-doped porous material is a particle of a porous carrier with metal microparticles and a plurality of hydroxyl groups on the surface of the porous carrier such that (i) the plurality of metal microparticles are attached to a first portion of the plurality of hydroxyl groups of the surface of the porous carrier and (ii) an amount of a phosphate-containing acid group or phosphate-containing acid groups can be bonded to a second portion of the plurality of hydroxyl groups of the surface of the porous carrier to form the modified catalyst.

Abstract: A data analysis system is provided in the invention. The data analysis system includes a storage device, a field-data-description-file generating module, and a general data readiness analysis module. The storage device stores a plurality of raw data. The field-data-description-file generating module generates the field-data-description files corresponding to the raw data. The general data readiness analysis module obtains a score of the consistency indicator of the raw data according to the field-data-description files. The general data readiness analysis module obtains the data of the category which needs to be analyzed from the raw data according to the category of each field-data-description file. The general data analysis module obtains the score of the completeness indicator, the score of the accuracy indicator, the score of the validity indicator, and the score of the compaction indicator which all correspond to the data of the category which needs to be analyzed.

Abstract: A gene editing system of Escherichia coli includes an Escherichia coli, a helper plasmid and a donor plasmid. The helper plasmid successively includes a transposase complex expression cassette, a Cas12k expression cassette, a first sgRNA cassette, a first antibiotic resistance gene and a first replication origin. The donor plasmid successively includes a left end sequence of a ShCAST transposon, an exogenous gene expression cassette, a right end sequence of the ShCAST transposon, a second sgRNA cassette, a second antibiotic resistance gene and a second replication origin.

Abstract: The present disclosure provides an ultrasonic drive and driving method configured for driving an ultrasonic tool. The ultrasonic drive includes a switch module, a sensing element and a control element. The sensing element senses the voltage and current of the ultrasonic tool and generates a sensing signal accordingly. The control element receives the sensing signal and outputs a control signal. The switch module outputs an ultrasonic signal according to the control signal for controlling the vibration of the ultrasonic tool. When the ultrasonic drive operates a frequency sweep function, the control element determines an operating interval and an operating frequency of the ultrasonic signal. When the ultrasonic drive operates a frequency following function, the control element adjusts the operating frequency according to the sensing signal for keeping the impedance of the ultrasonic tool consistent.

Abstract: A contactless charging system for smart garments having coils whose centroids are not colinear. Folding a coil in half through its centroid will null out its inductance. A smart garment having 3 coils that have centroids that are not colinear is proposed. Accordingly, there is no single folding line that intersects all 3 centroids thereby nullifying inductance. Power can be combined with one or more rectifiers such that power is not cancelled. The present disclosure is suitable for any charging environment or apparatus, such as, drawer or hanger.

Abstract: A contactless charging drawer for smart garments using magnetic coupling links. A frame with a primary coil creates a magnetic field which couples with a secondary coil disposed a drawer. Smart garments, or any device, can then be safely charged in the drawer. The combination provides for a wireless power charging environment while adding an extra degree of freedom in impedance transformation without the need for electrical contacts to the drawer.

Abstract: A workpiece quality analysis method includes: selecting an initial algorithm and a corresponding algorithm parameter combination from a plurality of preset algorithms; clustering a workpiece data into groups according to the initial algorithm and the algorithm parameter combination to obtain an initial model of the initial algorithm and a corresponding clustering result; obtaining a corresponding initial model evaluation index value according to the clustering result; selecting at least one parameter combination of another algorithm corresponding to the initial algorithm. According to the initial calculation, the method corresponds to the other algorithm parameter combination to group the workpiece data to obtain at least one other model and at least one other clustering result.

Abstract: A data analysis system is provided in the invention. The data analysis system includes a storage device, a field-data-description-file generating module, and a general data readiness analysis module. The storage device stores a plurality of raw data. The field-data-description-file generating module generates the field-data-description files corresponding to the raw data. The general data readiness analysis module obtains a score of the consistency indicator of the raw data according to the field-data-description files. The general data readiness analysis module obtains the data of the category which needs to be analyzed from the raw data according to the category of each field-data-description file. The general data analysis module obtains the score of the completeness indicator, the score of the accuracy indicator, the score of the validity indicator, and the score of the compaction indicator which all correspond to the data of the category which needs to be analyzed.