Patents by Inventor Chin-Wei Chen

Chin-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240159269
    Abstract: A rotary bearing assembly is disclosed and includes an input shaft, an inner-ring component, an outer-ring component and a load element. The input shaft is configured to combine a rotating shaft of a motor to provide a power input. The inner-ring component includes a gear set, wherein the inner-ring component is sleeved on the input shaft through the gear set and driven by the input shaft. The outer-ring component is sleeved on the inner-ring component through a load element and engaged with the gear set, wherein when the gear set is driven by the input shaft to drive the inner-ring component, the gear set drives the outer-ring component, and the inner-ring component and the outer-ring component are rotated relatively, wherein one of the inner-ring component and the outer-ring component is served to provide a power output, and a rotational speed difference is between the power input and the power output.
    Type: Application
    Filed: August 8, 2023
    Publication date: May 16, 2024
    Inventors: Chi-Wen Chung, Hung-Wei Lin, Hsien-Lung Tsai, Wei-Ying Chu, Chin-Hsiang Chen
  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Publication number: 20240127758
    Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.
    Type: Application
    Filed: May 23, 2023
    Publication date: April 18, 2024
    Inventors: Shinya Ono, Chin-Wei Lin, Chen-Ming Chen, Hassan Edrees
  • Patent number: 11961738
    Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta Chen, Hua-Tai Lin, Han-Wei Wu, Jiann-Yuan Huang
  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Publication number: 20240105518
    Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20240099086
    Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 21, 2024
    Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
  • Publication number: 20240088030
    Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.
    Type: Application
    Filed: January 23, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Liang CHEN, Chi-Yu LU, Ching-Wei TSAI, Chun-Yuan CHEN, Li-Chun TIEN
  • Publication number: 20230383399
    Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Ming-Yi SHEN, Hsin-Lin WU, Yao-Fong DAI, Pei-Yuan TAI, Chin-Wei CHEN, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN
  • Patent number: 11555271
    Abstract: The present invention relates to an artificial leather and a method for producing the same. The artificial leather includes a substrate, a thermoplastic polyurethane fiber adhesive layer, a thermoplastic polyurethane fiber layer, a paste layer, and a surface layer. The paste layer has a thermosetting paste or a high solid-content paste, and the paste has a specific adhesive temperature. A bonding can be performed at low temperature in the method for producing the same, and the artificial leather made by the method for producing the same has excellent hand feeling and/or smoothness.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 17, 2023
    Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.
    Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chien-Chia Huang, Chia-Ho Lin, Yen-Lun Tseng, Chin-Wei Chen, Ching-Lo Lin
  • Publication number: 20220275500
    Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Ming-Yi SHEN, Hsin-Lin WU, Yao-Fong DAI, Pei-Yuan TAI, Chin-Wei CHEN, Yin-Tun CHOU, Yuan-Hsin CHI, Sheng-Yuan LIN
  • Publication number: 20210262161
    Abstract: The present invention relates to an artificial leather and a method for producing the same. The artificial leather includes a substrate, a thermoplastic polyurethane fiber adhesive layer, a thermoplastic polyurethane fiber layer, a paste layer, and a surface layer. The paste layer has a thermosetting paste or a high solid-content paste, and the paste has a specific adhesive temperature. A bonding can be performed at low temperature in the method for producing the same, and the artificial leather made by the method for producing the same has excellent hand feeling and/or smoothness.
    Type: Application
    Filed: November 16, 2020
    Publication date: August 26, 2021
    Inventors: Chih-Yi LIN, Kuo-Kuang CHENG, Chien-Chia HUANG, Chia-Ho LIN, Yen-Lun TSENG, Chin-Wei CHEN, Ching-Lo LIN
  • Patent number: 10841228
    Abstract: An abnormal flow detection device and an abnormal flow detection method thereof are provided. The abnormal flow detection device analyses a plurality of packets captured during a time interval to obtain a plurality of flow features of each packet and selects at least one key flow feature from the flow features based on a dimensionality reduction algorithm. The abnormal flow detection device trains a bidirectional generative adversarial network (BiGAN) by taking the at least one key flow feature of each packet as an input of the BiGAN to build a flow recognition model for detecting abnormal flows.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 17, 2020
    Assignee: Institute For Information Industry
    Inventors: Kun-Wei Lee, Chin-Wei Chen, Te-En Wei, Hsiao-Hsien Chang
  • Publication number: 20200153742
    Abstract: An abnormal flow detection device and an abnormal flow detection method thereof are provided. The abnormal flow detection device analyses a plurality of packets captured during a time interval to obtain a plurality of flow features of each packet and selects at least one key flow feature from the flow features based on a dimensionality reduction algorithm. The abnormal flow detection device trains a bidirectional generative adversarial network (BiGAN) by taking the at least one key flow feature of each packet as an input of the BiGAN to build a flow recognition model for detecting abnormal flows.
    Type: Application
    Filed: December 5, 2018
    Publication date: May 14, 2020
    Inventors: Kun-Wei LEE, Chin-Wei CHEN, Te-En WEI, Hsiao-Hsien CHANG
  • Publication number: 20180036861
    Abstract: The present invention relates to a polishing pad with improved slurry retention capacity, which includes a polishing layer. The polishing layer includes an elastomer main body and a plurality of titanium dioxide nanowires. Each of the titanium dioxide nanowires is independent and is distributed evenly and randomly in the elastomer main body. The present invention further provides a polishing apparatus and a method for manufacturing the polishing pad.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 8, 2018
    Inventors: CHUNG-CHIH FENG, I-PENG YAO, YUNG-CHANG HUNG, PIN-HSIEN SUNG, CHIN-WEI CHEN, WEN-CHIEH WU
  • Publication number: 20150157473
    Abstract: An artificial knee joint is to be connected between a prosthetic thigh and a prosthetic lower leg. The artificial knee joint includes a knee joint body, a processor mounted in the knee joint body, a damping unit that is coupled to the processor and configurable to provide various damping levels, and an accelerometer coupled to the processor. The accelerometer is configured to measure acceleration subjected to the artificial knee joint, and to generate and transmit a measuring signal according to the measurement to the processor. The processor is configured to control the damping unit to provide one of the damping levels, based on the measuring signal.
    Type: Application
    Filed: October 8, 2014
    Publication date: June 11, 2015
    Inventors: Hung-Jen Lai, Ying-Ming Chung, Jian-Liang Chen, Chin-Wei Chen, Chen-Hsien Chang, Jian-Hong Lin, Jian-Yu Chen
  • Patent number: D883966
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 12, 2020
    Assignee: WISTRON NEWEB CORP.
    Inventors: Bau-Yi Huang, Chin-Wei Chen
  • Patent number: D883967
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 12, 2020
    Assignee: WISTRON NEWEB CORP.
    Inventors: Bau-Yi Huang, Chin-Wei Chen
  • Patent number: D1018537
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: March 19, 2024
    Assignee: HTC CORPORATION
    Inventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen
  • Patent number: D1026910
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: May 14, 2024
    Assignee: HTC CORPORATION
    Inventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen