Patents by Inventor Chin-Wei Lee

Chin-Wei Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12262647
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: March 1, 2024
    Date of Patent: March 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20250079334
    Abstract: A semiconductor package may include a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, and a reinforcement structure mechanically coupled to at least a first vertical surface of the first semiconductor die and a second vertical surface of the second semiconductor die, such that the reinforcement structure surrounds less than an entirety of the first semiconductor die and the second semiconductor die. The semiconductor package may include an underfill material formed between a top surface of the package substrate and bottom surfaces of the first semiconductor die and the second semiconductor die. The reinforcement structure may include a polymer material located in a space between the first semiconductor die and the second semiconductor die. The polymer material may be a polymer matrix composite having a greater modulus than the underfill material.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Yu Chen Lee, Chin-Hua Wang, Chun-Wei Chen, Shin-Puu Jeng
  • Publication number: 20250070046
    Abstract: An integrated circuit includes a semiconductor substrate, an interconnection structure, a first dielectric layer, conductive pads, a second dielectric layer, conductive connectors, and an anti-stress layer. The interconnection structure is disposed on the semiconductor substrate. The first dielectric layer is disposed on the interconnection structure. The conductive pads are disposed on the first dielectric layer and are electrically connected to the interconnection structure. The second dielectric layer is disposed on the first dielectric layer to laterally surround the conductive pads. The conductive connectors are disposed on and electrically connected to the conductive pads. The anti-stress layer is disposed over the conductive pads and laterally surrounds some of the conductive connectors.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cong-Wei Yang, Yu Chen Lee, Chin-Hua Wang, Shin-Puu Jeng
  • Publication number: 20250071935
    Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Chin-Ting Chen, Chih-Wei Yang, Shu-Cheng Yang, Che-Wei Chang, Wen-Cheng Huang, Chin-Hung Lee, Chih-Wei Chan
  • Publication number: 20250062176
    Abstract: A device structure includes: an interposer including interposer dielectric material layers having formed therein interposer metal interconnect structures and die-side interposer bonding pads; at least one semiconductor die having formed therein in-die bonding pads that are bonded to a respective one of the die-side interposer bonding pads by metal-to-metal bonding; and a composite die frame laterally surrounding the at least one semiconductor die. The composite die frame includes a molding compound die frame portion including a molding compound material and frame edge reinforcement structures located at corners of the composite die frame and including a material having a lower coefficient of thermal expansion at 20 degrees Celsius than the molding compound material.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 20, 2025
    Inventors: Chin-Hua Wang, Tsung-Yen Lee, Cong-Wei Yang, Shin-Puu Jeng
  • Publication number: 20060175044
    Abstract: A heat dissipating tube with copper powders comprises a metal tube; an inner wall of the metal tube having at least one non-flat portion; and a plurality of copper powders adhered on the inner wall of the metal tube. There are a plurality of non-flat portions which are distributed along a periphery of a cross section of the metal tube. A cross section of the non-flat portion has a shape selected from one of trapezoids, rectangular shapes, semi-round shapes, sector shapes, sawtooth shapes, triangular shapes, or other irregular shape. The non-flat portion may be selected from one of at least one trench, at least one protrusion and at least one groove.
    Type: Application
    Filed: February 10, 2005
    Publication date: August 10, 2006
    Inventors: Chin-Wei Lee, Ping-Huang Yang