Patents by Inventor Chin-Wei Liang
Chin-Wei Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
-
Patent number: 11887929Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.Type: GrantFiled: July 20, 2022Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsing-Lien Lin, Chin-Wei Liang, Hsun-Chung Kuang, Ching Ju Yang
-
Patent number: 11869916Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.Type: GrantFiled: November 13, 2020Date of Patent: January 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang, Sheng-Chan Li
-
Publication number: 20230378225Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.Type: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Inventors: Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang, Sheng-Chan Li
-
Publication number: 20220367342Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Hsing-Lien Lin, Chin-Wei Liang, Hsun-Chung Kuang, Ching Ju Yang
-
Patent number: 11495532Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.Type: GrantFiled: October 23, 2020Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsing-Lien Lin, Chin-Wei Liang, Hsun-Chung Kuang, Ching Ju Yang
-
Publication number: 20220285156Abstract: An apparatus for wafer bonding includes a transfer module and a plasma module. The transfer module is configured to transfer a semiconductor wafer. The plasma module is configured to apply a first type of plasma to perform a reduction operation upon a surface of the semiconductor wafer at a temperature within a predetermined temperature range to convert metal oxides on the surface of the semiconductor wafer to metal, and apply a second type of plasma to perform a plasma operation upon the surface of the semiconductor wafer at a room temperature outside the predetermined temperature range to activate a surface of the semiconductor wafer.Type: ApplicationFiled: May 26, 2022Publication date: September 8, 2022Inventors: YEONG-JYH LIN, YEUR-LUEN TU, CHIN-WEI LIANG
-
Patent number: 11404484Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.Type: GrantFiled: August 14, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
-
Patent number: 11348790Abstract: An apparatus for wafer bonding includes a transfer module and a plasma module. The transfer module is configured to transfer a semiconductor wafer. The plasma module is configured to apply a first type of plasma to perform a reduction operation upon a surface of the semiconductor wafer at a temperature within a predetermined temperature range to convert metal oxides on the surface of the semiconductor wafer to metal, and apply a second type of plasma to perform a plasma operation upon the surface of the semiconductor wafer at a room temperature outside the predetermined temperature range to activate a surface of the semiconductor wafer.Type: GrantFiled: April 27, 2020Date of Patent: May 31, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yeong-Jyh Lin, Yeur-Luen Tu, Chin-Wei Liang
-
Publication number: 20220157875Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang, Sheng-Chan Li
-
Publication number: 20210327748Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.Type: ApplicationFiled: June 28, 2021Publication date: October 21, 2021Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
-
Patent number: 11133231Abstract: A method for estimating film thickness in CMP includes the following operations. A substrate with a film formed thereon is disposed over a polishing pad with a slurry dispensed between the film and the polishing pad. A CMP operation is performed to reduce a thickness of the film. An in-situ electrochemical impedance spectroscopy (EIS) measurement is performed during the CMP operation by an EIS device to estimate the thickness of the film real-time. The CMP operation is ended when the estimated thickness of the film obtained from the fit parameters of the first equivalent electrical circuit model reaches a target thickness.Type: GrantFiled: March 27, 2018Date of Patent: September 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Min Chen, Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang
-
Publication number: 20210272896Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.Type: ApplicationFiled: October 23, 2020Publication date: September 2, 2021Inventors: Hsing-Lien Lin, Chin-Wei Liang, Hsun-Chung Kuang, Ching Ju Yang
-
Patent number: 11049767Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.Type: GrantFiled: September 26, 2019Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsai-Ming Huang, Wei-Chieh Huang, Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Che Chung, Chin-Wei Liang, Ching-Sen Kuo, Jieh-Jang Chen, Feng-Jia Shiu, Sheng-Chau Chen
-
Patent number: 11024800Abstract: Various embodiments of the present disclosure are directed towards a memory cell. The memory cell includes a bottom electrode overlying a substrate. A data storage structure overlies the bottom electrode. A top electrode overlies the data storage structure. Sidewalls of the top electrode and sidewall of the bottom electrode are aligned. Further, a getter layer abuts the bottom electrode.Type: GrantFiled: January 23, 2020Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hai-Dang Trinh, Chin-Wei Liang, Hsing-Lien Lin, Fa-Shen Jiang
-
Patent number: 10967479Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) pad, and an associated method to perform a CMP process. In some embodiments, the CMP pad comprises a polishing layer having a front surface with protruding asperities while a back surface being planar. A film electrode is attached to the back surface of the polishing layer and is isolated from the front surface of the polishing layer. The CMP pad further comprises an insulating layer covering sidewall and bottom surfaces of the film electrode.Type: GrantFiled: June 13, 2019Date of Patent: April 6, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Wei Liang, Hsun-Chung Kuang, Yen-Chang Chu
-
Patent number: 10910260Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.Type: GrantFiled: October 25, 2019Date of Patent: February 2, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Hsia-Wei Chen, Jieh-Jang Chen, Ching-Sen Kuo
-
Publication number: 20200373357Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.Type: ApplicationFiled: August 14, 2020Publication date: November 26, 2020Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin
-
Patent number: 10818857Abstract: The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material.Type: GrantFiled: December 19, 2017Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Wei Liang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
-
Patent number: 10748967Abstract: Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.Type: GrantFiled: June 25, 2018Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Wei Liang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin