Patents by Inventor Chin-Wei Lin

Chin-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12388021
    Abstract: Methods for selectively depositing a metal layer over a gate structure and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate structure over the channel region; a gate spacer adjacent the gate structure; a first dielectric layer adjacent the gate spacer; a barrier layer contacting a top surface of the gate spacer and a side surface of the first dielectric layer, the barrier layer including a nitride; and a metal layer over the gate structure adjacent the barrier layer, the metal layer having a first width equal to a second width of the gate structure.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: August 12, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Hsien Lin, Ting-Gang Chen, Chin-Wei Lin, Chi On Chui
  • Publication number: 20250231580
    Abstract: A display may include an array of pixels that receive row control signals from gate driver circuitry. The gate driver circuitry can include a chain of gate drivers configured to receive one or more clock signals. The gate driver circuitry can further include inverters configured to invert the one or more clock signals to generate inverted clock signals. The clock signals and the inverted clock signals can be conveyed to the chain of gate drivers. Falling edges of the clock signals and the inverted clock signals can be used to trigger assertions and deassertions of the row control signals. Operated in this way, the power consumption of the gate driver circuitry can be reduced.
    Type: Application
    Filed: October 30, 2024
    Publication date: July 17, 2025
    Inventors: Gihoon Choo, Tsung-Ting Tsai, Shyuan Yang, Abbas Jamshidi Roudbari, Chin-Wei Lin, Mao-Hsun Cheng, Salman Kabir, Ting-Kuo Chang, Warren S. Rieutort-Louis, Yuchi Che, Qing Li, Cheng-Chih Hsieh
  • Patent number: 12327519
    Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor coupled in series with an isolation transistor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations. During a data refresh, the isolation transistor can be turned on to provide current boosting. During emission periods, the isolation transistor is turned off to prevent cathode noise from potentially coupling through to one or more direct-current voltage nodes in the pixel.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: June 10, 2025
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Aida R Colon-Berrios, Fan Gui, Levent Erdal Aygun, Mohammad Reza Esmaeili Rad, Ran Tu, Xin Lin, Yun Wang
  • Patent number: 12322330
    Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.
    Type: Grant
    Filed: October 9, 2023
    Date of Patent: June 3, 2025
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Shyuan Yang, Chuang Qian, Abbas Jamshidi Roudbari, Ting-Kuo Chang
  • Publication number: 20250174497
    Abstract: A die-level parametric prediction boosting method includes acquiring a wafer map having a plurality of dies, selecting a die from the plurality of dies, inputting physical location parametric data of the die and a plurality of electrical parametric features of the die to a training model, and generating predicted data of the die by the training model according to the physical location parametric data and the plurality of electrical parametric features.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 29, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chin-Wei Lin, Po-Chao Tsao, Yu-Lin Yang, Cheng-Tien Wan, Tung-Hsing Lee, Chung-Kai Chang, Yi-Ju Ting, Chia-Jung Ni, Chia-Chun Sun, Cheng-Chien Huang, Yun-San Huang, Ming-Cheng Lee
  • Publication number: 20250174498
    Abstract: A die-level parametric prediction boosting method includes acquiring mass production data of a plurality of dies, identifying a comprehensive indicator of each die according to the mass production data, generating a wafer map distribution of the plurality of dies according to a plurality of comprehensive indicators, partitioning the plurality of dies into at least two die clustering groups, and inputting a plurality of electrical parametric features of each die clustering group to a training model for generating predicted data of each die clustering group.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 29, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chin-Wei Lin, Chi-Ming Lee, Po-Chao Tsao, Tsung-Te Chen, Khim Jun Koh, Yu-Lin Yang, Cheng-Tien Wan, Yi-Ju Ting, Tung-Hsing Lee
  • Publication number: 20250148273
    Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 8, 2025
    Inventors: Khim Jun Koh, Chi-Ming Lee, Yi-Ju Ting, Chung-Kai Chang, Po-Chao Tsao, Chin-Wei Lin, Yu-Lin Yang, Tung-Hsing Lee, Chin-Tang Lai
  • Publication number: 20250148271
    Abstract: An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.
    Type: Application
    Filed: October 15, 2024
    Publication date: May 8, 2025
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Po-Chao Tsao, Hsiang-An Chen, Chin-Wei Lin, Ming-Cheng Lee, Tung-Hsing Lee
  • Publication number: 20250148969
    Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Vasudha Gupta, Shinya Ono, Tsung-Ting Tsai, Shyuan Yang
  • Publication number: 20250131885
    Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.
    Type: Application
    Filed: January 9, 2024
    Publication date: April 24, 2025
    Inventors: Shinya Ono, Chin-Wei Lin, Chen-Ming Chen, Hassan Edrees
  • Publication number: 20250037672
    Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.
    Type: Application
    Filed: October 18, 2024
    Publication date: January 30, 2025
    Inventors: Shinya Ono, Chin-Wei Lin, Zino Lee, Chun-Chieh Lin, Chen-Ming Chen
  • Publication number: 20250040358
    Abstract: An organic light-emitting diode display may have thin-film transistor circuitry formed on a substrate. The display and substrate may have rounded corners. A pixel definition layer may be formed on the thin-film transistor circuitry. Openings in the pixel definition layer may be provided with emissive material overlapping respective anodes for organic light-emitting diodes. A cathode layer may cover the array of pixels. A ground power supply path may be used to distribute a ground voltage to the cathode layer. The ground power supply path may be formed from a metal layer that is shorted to the cathode layer using portions of a metal layer that forms anodes for the diodes, may be formed from a mesh shaped metal pattern, may have L-shaped path segments, may include laser-deposited metal on the cathode layer, and may have other structures that facilitate distribution of the ground power supply.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Chin-Wei Lin, Stephen S. Poon, Warren S. Rieutort-Louis, Cheng-Ho Yu, ChoongHo Lee, Doh-Hyoung Lee, Ting-Kuo Chang, Tsung-Ting Tsai, Vasudha Gupta, Younggu Lee
  • Patent number: 12205531
    Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: January 21, 2025
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Vasudha Gupta, Shinya Ono, Tsung-Ting Tsai, Shyuan Yang
  • Patent number: 12207512
    Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: January 21, 2025
    Assignee: Apple Inc.
    Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
  • Publication number: 20250022423
    Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
    Type: Application
    Filed: October 2, 2024
    Publication date: January 16, 2025
    Inventors: Chin-Wei Lin, Hung Sheng Lin, Shih Chang Chang, Shinya Ono
  • Patent number: 12189171
    Abstract: A display apparatus including a display panel, a first light source module, and a second light source module is disclosed. The display panel has a display surface and a back surface away from the display surface. The first light source module is disposed on a side of one of the display surface and the back surface of the display panel, and overlaps the display surface. The second light source module is disposed on a side of the other one of the display surface and the back surface of the display panel, and overlaps the display surface.
    Type: Grant
    Filed: November 26, 2023
    Date of Patent: January 7, 2025
    Assignee: HannStar Display Corporation
    Inventors: Chen-Hao Su, Chin-Wei Lin, Chin-Yung Liu
  • Publication number: 20240420644
    Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a mix of silicon transistors, one or more semiconducting oxide transistors, and one or more capacitors. The semiconducting oxide transistors can each have a back gate terminal shorted to one of its source-drain terminals, shorted to its front gate terminal, or configured to receive a bias voltage. Configured in this way, the gate driver circuit can exhibit less threshold voltage drift and thus improved device reliability over time.
    Type: Application
    Filed: May 8, 2024
    Publication date: December 19, 2024
    Inventors: Fan Gui, Chin-Wei Lin, Aida R Colon-Berrios, Ran Tu, Xuan Hu, Levent Erdal Aygun, Yi Zhao
  • Publication number: 20240420646
    Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Inventors: Shinya Ono, Chin-Wei Lin, Chen-Ming Chen, Hassan Edrees
  • Publication number: 20240420643
    Abstract: A driver circuit configured to output a control signal to a row of display pixels is provided. The driver circuit can include a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit on which the control signal is generated and a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line. The first and second transistors can be coupled to a plurality of transistors coupled between a second positive power supply line and a second ground power supply line, configured to receive one or more clocks signals, and at least some of which include bottom gate terminals.
    Type: Application
    Filed: May 3, 2024
    Publication date: December 19, 2024
    Inventors: Hao-Lin Chiu, Chin-Wei Lin, Shinya Ono, Kyung Wook Kim, Szu-Hsien Lee, Pei-En Chang, Kwang Soon Park
  • Patent number: RE50396
    Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels, that include hybrid thin-film transistor structures formed using semiconducting-oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. A drive transistor in the display pixel may be a top-gate semiconducting-oxide thin-film transistor and a switching transistor in the display pixel may be a top-gate silicon thin-film transistor. A storage capacitor in the display may include a conductive semiconducting-oxide electrode.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 22, 2025
    Assignee: Apple Inc.
    Inventors: Shinya Ono, Chin-Wei Lin, Ching-Sang Chuang, Jiun-Jye Chang, Keisuke Omoto, Shang-Chih Lin, Ting-Kuo Chang, Takahide Ishii