Patents by Inventor Chin Wei Wu

Chin Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Patent number: 11961738
    Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta Chen, Hua-Tai Lin, Han-Wei Wu, Jiann-Yuan Huang
  • Publication number: 20240118316
    Abstract: A probe card and a manufacturing method of a probe card are provided. The probe card includes a probe head, first and second substrates, an insulating component, and an adhesive member. The second substrate is disposed between the probe head and the first substrate, and is disposed on the first substrate. The second substrate faces the first substrate and includes second contacts. The second contacts are electrically connected to first contacts of the first substrate. The insulating component is disposed between the first substrate and the second substrate, and disposed at an outer side of the second contacts. The adhesive member is disposed on the first substrate, arranged on at least a part of the side surface of the second substrate, and disposed at an outer side of the insulating component.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Applicant: MPI Corporation
    Inventors: Chin-Yi Lin, Che-Wei Lin, Ting-Ju Wu, Chien-Kai Hung
  • Patent number: 11956563
    Abstract: A method for identifying video signal source is provided. The method includes the following steps. A first identification code is assigned to a first transmitter device by a receiver control unit of a receiver device. A first video data is transmitted by the first transmitter device. The first video data and a first identification image corresponding to the first identification code are combined as a first combined video data by the receiver control unit. The first combined video data is outputted to a display device by the receiver control unit.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 9, 2024
    Assignee: BenQ Corporation
    Inventors: Chia-Nan Shih, Chen-Chi Wu, Lin-Yuan You, Chin-Fu Chiang, Ron-Kun Tseng, Chuang-Wei Wu
  • Publication number: 20240105518
    Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20240083742
    Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li YANG, Kai-Di WU, Ming-Da CHENG, Wen-Hsiung LU, Cheng Jen LIN, Chin Wei KANG
  • Patent number: 10324034
    Abstract: A self-referencing localized plasmon resonance sensing device and a system thereof are disclosed. The reference optical waveguide element is modified with a noble metal nanoparticle layer. The sensing optical waveguide element is modified with a noble metal nanoparticle layer, which is further modified with a recognition unit. The incident light is guided into the reference and the sensing optical waveguide elements to respectively generate localized plasmon resonance sensor signals. The reference and the sensing optical waveguide elements respectively have a calibration slope. The processor utilizes the calibration slopes to regulate the second difference generated by detecting with the sensing optical waveguide element. The processor utilizes a difference between the first difference, which is generated by detecting with the reference optical waveguide element, and the regulated second difference to obtain a sensor response.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 18, 2019
    Assignee: National Chung Cheng University
    Inventors: Lai-Kwan Chau, Chin-Wei Wu, Chang-Yue Chiang, Chien-Hsing Chen
  • Publication number: 20190013204
    Abstract: A method of fabricating a buried word line includes forming a trench in a substrate. Next, a deposition process is performed to form a silicon layer on a sidewall and a bottom at the inner side of the trench. After the deposition process, a gate dielectric layer is formed in the trench. Finally, a conductive layer is formed to fill in the trench.
    Type: Application
    Filed: July 26, 2017
    Publication date: January 10, 2019
    Inventors: Tien-Chen Chan, Ger-Pin Lin, Tsuo-Wen Lu, Chin-Wei Wu, Yu-Chun Wang, Shu-Yen Chan
  • Patent number: 10056288
    Abstract: A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the active area. The gate trench exposes a sidewall of the active area and a sidewall of the trench isolation region. The sidewall of the trench isolation region includes a void. A first gate dielectric layer conformally covers the sidewall of the active area and the sidewall of the trench isolation region. The void in the sidewall of the trench isolation region is filled with the first gate dielectric layer. A second gate dielectric layer is grown on the sidewall of the active area. A gate is embedded in the gate trench.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 21, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsuo-Wen Lu, Chin-Wei Wu, Tien-Chen Chan, Ger-Pin Lin, Shu-Yen Chan
  • Patent number: 9394320
    Abstract: A method for fixing metal onto a surface of the substrate. The present method includes steps of: providing a substrate and a mercaptoalkylsilatrane compound; dissolving the mercaptoalkylsilatrane compound in a solvent; performing a condensation reaction of the substrate with and the dissolved mercaptoalkylsilatrane compound to complete the surface modification of the substrate; and performing a covalent bonding process to metal with the mercaptoalkylsilatrane compound already modified onto the surface of the substrate to fix the metal onto the surface of the substrate.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: July 19, 2016
    Assignee: National Chung Cheng University
    Inventors: Lai-Kwan Chau, Wen-Hao Chen, Yen-Ta Tseng, Chin-Wei Wu, Chao-Wen Chen
  • Publication number: 20160169797
    Abstract: A self-referencing localized plasmon resonance sensing device and a system thereof are disclosed. The reference optical waveguide element is modified with a noble metal nanoparticle layer. The sensing optical waveguide element is modified with a noble metal nanoparticle layer, which is further modified with a recognition unit. The incident light is guided into the reference and the sensing optical waveguide elements to respectively generate localized plasmon resonance sensor signals. The reference and the sensing optical waveguide elements respectively have a calibration slope. The processor utilizes the calibration slopes to regulate the second difference generated by detecting with the sensing optical waveguide element. The processor utilizes a difference between the first difference, which is generated by detecting with the reference optical waveguide element, and the regulated second difference to obtain a sensor response.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Inventors: Lai-Kwan CHAU, Chin-Wei WU, Chang-Yue CHIANG, Chien-Hsing CHEN
  • Publication number: 20140295075
    Abstract: A method for fixing metal onto a surface of the substrate. The present method includes steps of: providing a substrate and a mercaptoalkylsilatrane compound; dissolving the mercaptoalkylsilatrane compound in a solvent; performing a condensation reaction of the substrate with and the dissolved mercaptoalkylsilatrane compound to complete the surface modification of the substrate; and performing a covalent bonding process to metal with the mercaptoalkylsilatrane compound already modified onto the surface of the substrate to fix the metal onto the surface of the substrate.
    Type: Application
    Filed: March 17, 2014
    Publication date: October 2, 2014
    Applicant: National Chung Cheng University
    Inventors: Lai-Kwan Chau, Wen-Hao Chen, Yen-Ta Tseng, Chin-Wei Wu, Chao-Wen Chen
  • Patent number: 8192251
    Abstract: A pressure control system of a wafer polishing apparatus includes a main input air pressure regulator, an air branch conduit, a plurality of first pipes, a plurality of auxiliary air pressure regulators, a plurality of second pipes, and a plurality of air pressure controlling devices. The air branch conduit is connected with the main input air pressure regulator. The first pipes are connected between the air branch conduit and the auxiliary air pressure regulators. The second pipes are connected between the auxiliary air pressure regulators and the air pressure controlling devices. Accordingly, the air pressure controlling devices can control the pressure outputted from a polishing head of the wafer polishing apparatus to a surface of a wafer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: June 5, 2012
    Assignee: Inotera Memories, Inc.
    Inventors: Yueh Cheng Hsueh, Chin Wei Wu, Sheng-Feng Hung
  • Publication number: 20100203807
    Abstract: A pressure control system of a wafer polishing apparatus includes a main input air pressure regulator, an air branch conduit, a plurality of first pipes, a plurality of auxiliary air pressure regulators, a plurality of second pipes, and a plurality of air pressure controlling devices. The air branch conduit is connected with the main input air pressure regulator. The first pipes are connected between the air branch conduit and the auxiliary air pressure regulators. The second pipes are connected between the auxiliary air pressure regulators and the air pressure controlling devices. Accordingly, the air pressure controlling devices can control the pressure outputted from a polishing head of the wafer polishing apparatus to a surface of a wafer.
    Type: Application
    Filed: July 8, 2009
    Publication date: August 12, 2010
    Inventors: Yueh Cheng Hsueh, Chin Wei Wu, Sheng-Feng Hung