Patents by Inventor Chin-Wen Lee

Chin-Wen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7419872
    Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 2, 2008
    Assignee: Promos Technologies, Inc.
    Inventors: Ching Lee, Chin Wen Lee, Chin Long Hung, Zheng Cheng Chen
  • Publication number: 20080096346
    Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
    Type: Application
    Filed: November 21, 2006
    Publication date: April 24, 2008
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: Ching Lee, Chin Wen Lee, Chin Long Hung, Zheng Cheng Chen
  • Publication number: 20080081444
    Abstract: A method for forming a silicide layer on a silicon surface is provided. First, inert gas ions are implanted into the silicon surface. Then, a metal layer is formed on the surface and subsequently converted into the suicide layer. Thereby the resistance of the silicide can be reduced and the uniformity can be raised without substantially altering the doping concentration of conductive component(s). Thus, the efficiency of the semiconductor device can be enhanced.
    Type: Application
    Filed: November 14, 2006
    Publication date: April 3, 2008
    Applicant: Promos Technologies Inc.
    Inventor: Chin-Wen Lee
  • Patent number: 6720885
    Abstract: The present invention provides a method for signal vibration alert. The method of the present invention recognizes significant substantial swerves and corresponding substantial edge-to-edge differences by eliminating the adverse effect of noise among signals generated by an apparatus. When the frequency of the substantial edge-to-edge differences that exceed an acceptable range of the frequency limit is too large, the method of the present invention automatically generates an alert to indicate aberration in the apparatus such that the monitoring staff is informed and allowed to take necessary measures responding to the aberration.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: April 13, 2004
    Assignee: ProMOS Technologies Inc.
    Inventors: Chin-Wen Lee, Hung-Wen Chiou