Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: An object of the present disclosure is at least to provide a cell fusion method having a high cell fusion rate. The object is solved by a cell fusion method including pressurizing, by a pressurization portion, a solution containing multiple cells of one or more types and at least one type of chemical cell fusion agent, the solution contained in a container portion.

Abstract: A smart module card and using method thereof are provided. The smart module card can be implemented in a peripheral platform having a transmitting port. The smart module includes a connecting port and a processing unit electrically connected thereto. The connecting port corresponds to the transmitting port, and the processing unit includes a plurality of functional chips. When the connecting port is electrically connected to the transmitting port, the processing unit receives an identification data provided by the peripheral platform to determine a plurality of predetermined operating functions required by the peripheral platform to be enabled, and the processing unit executes some of the functional chips to correspondingly enable the predetermined operating functions.

Abstract: A smart module card and using method thereof are provided. The smart module card can be implemented in a peripheral platform having a transmitting port. The smart module includes a connecting port and a processing unit electrically connected thereto. The connecting port corresponds to the transmitting port, and the processing unit includes a plurality of functional chips. When the connecting port is electrically connected to the transmitting port, the processing unit receives an identification data provided by the peripheral platform to determine a plurality of predetermined operating functions required by the peripheral platform to be enabled, and the processing unit executes some of the functional chips to correspondingly enable the predetermined operating functions.

Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.