Abstract: Methods are provided for forming a contoured floating gate for use in a floating gate memory cell. One method includes forming a floating gate that has a polysilicon layer over a substrate, forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.

Abstract: A floating gate for use in a memory cell is provided which comprises a first end region adjacent a first lateral end of the floating gate; a second end region adjacent a second lateral end of the floating gate opposite the first lateral end; and a middle region positioned laterally between the first and second end regions, the middle region having a vertical thickness which is less than a vertical thickness of the first end region and which is less than a vertical thickness of the second end region; wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first and second end regions and middle region by one or more subsequent fabrication steps.

Abstract: Systems and methods are described for providing an array of buried transistor cells with at least one contact array structure. A contact array structure for a buried type transistor array includes a first diffusion bit line coupled to the plurality of transistors; a first plurality of contacts coupled to the source diffusion bit line; and a first conductor coupled to the first plurality of contacts. The systems and methods provide advantages in that the diffusion line resistance is reduced, the read current and speed are reduced, and the voltage-time distribution is tightened when writing by hot electron programming.

Abstract: A floating gate having a first and second end region, each of which are positioned adjacent to a corresponding lateral end of the floating gate. A middle region is positioned laterally towards a middle of the floating gate relative to the first and second end regions. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region formed has a thickness which is less than a thickness of the first or second end regions. This invention further includes a method for forming a contoured floating gate for use in a floating gate memory cell.

Abstract: A semiconductor wafer is provided, the semiconductor wafer including a substrate, a first polysilicon layer having an approximately rectangular cross-section positioned on the substrate, and a sacrificial layer positioned on the first polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upper portion of the sidewalls of the sacrificial layer. Following this, a passivation layer is formed on the surface of the dielectric layer and contacts the exposed sidewalls of the upper portion of the sacrificial layer. Then, both the passivation layer and the dielectric layer positioned over the sacrificial layer are removed down to a predetermined height by CMP. The dielectric layer is removed from the sacrificial layer followed by removing the passivation layer from the surface of the semiconductor wafer and removing the sacrificial layer from the first polysilicon layer.

Abstract: A floating gate for use in a memory cell is provided which comprises a first end region adjacent a first lateral end of the floating gate; a second end region adjacent a second lateral end of the floating gate opposite the first lateral end; and a middle region positioned laterally between the first and second end regions, the middle region having a vertical thickness which is less than a vertical thickness of the first end region and which is less than a vertical thickness of the second end region; wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first and second end regions and middle region by one or more subsequent fabrication steps.

Abstract: The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell.

Abstract: A detachable table and chair assembly includes a table, a vertical bumper panel attached to a leading end of the table, a chair and parallel side bars movably connecting the chair to a rear end of the table. The table has spaced apart side panels mounted securely on a leading end of the side bars, and a table top mounted on a top end of the side panels. The table top has a hollow bottom part which defines a first receiving space, and a flat top part which covers the first receiving space. The chair has spaced apart side panels mounted movably on a rear end of the side bars and spaced apart transverse panels formed between the chair side panels to define a second receiving space. A seat panel is supported on the chair side panels and pivotable between a first position to close the second receiving space and a second position to access the second receiving space.

Abstract: In accordance with the present invention, there are provided lipid-conjugated polyamide compounds and related compositions and methods thereof. Lipid-conjugated polyamide compounds of the present invention are particularly useful as vehicles for delivering biologically active agents to a target site. In particular, the invention compounds are effective at facilitating the delivery of polynucleotides to cells. The present invention also provides a method for producing stable formulations of polynucleotides complexed with a delivery vehicle.

Abstract: The invention relates to a shallow trench isolation method used in a semiconductor wafer that comprises a plurality of predetermined active regions, a plurality of shallow trenches used for electrically isolating the plurality of active regions, and a wafer alignment region wherein at least one recess having a predetermined pattern is formed on the surface of the wafer. In the method of the present invention, an insulation layer is first formed on the surface of the semiconductor wafer to fill the recesses in the wafer alignment region and the plurality of shallow trenches. An etching process is then implemented to reduce the thickness of the insulation layer on the surface of the working region, the working region having a relatively high density of active regions. Also, the insulation layer is completely removed from the recesses within the wafer alignment region.

Abstract: A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.

Abstract: The present invention provides a method and an apparatus for programming a selected call within a virtual ground EPROM array cell without disturbing adjacent array cells.

Abstract: A process is provided for fabricating a nonvolatile memory cell. According to the process, source and drain regions are formed on a first conductivity-type semiconductor substrate; and insulating layer is formed on the source and drain regions; a floating gate is formed on the insulating layer; a dielectric composite is formed on the floating gate; and a control gate is formed on the dielectric composite. The dielectric composite includes a bottom layer of silicon dioxide formed on the floating gate; a layer of silicon nitride formed on the bottom silicon dioxide layer; and a top layer of silicon dioxide formed on the nitride layer such that the silicon nitride layer of the composite is thinner than the top or the bottom silicon dioxide layer.

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a nonvolatile memory cell such as EPROM, EEPROM and flash EPROM cells is provided which includes a bottom layer of silicon dioxide formed on the floating gate, a layer of silicon nitride formed on the bottom silicon dioxide layer and a top silicon dioxide layer formed on the nitride layer where the silicon nitride layer has a thickness in the resulting composite which is less than the bottom and top silicon dioxide layers. In one embodiment, the nonvolatile memory cell includes a first conductivity-type semiconductor substrate, source and drain regions formed on a surface of the substrate, an insulating layer thermally grown on top of the source and drain regions, a floating gate positioned on the insulating layer for insulating the floating gate from the source and drain regions, the dielectric insulating composite being positioned between the floating gate and a control gate.