Abstract: A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.

Abstract: A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

Abstract: A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.

Abstract: A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

Abstract: A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.

Abstract: A flash memory control technique with high reliability is provided. A flash memory controller provides a volatile storage area for temporary storage of logical-to-physical address mapping data between a host and a flash memory as well as error detection codes encoded from the logical-to-physical address mapping data. When reading from the volatile storage area, the microcontroller of the flash memory controller is configured to perform an error detection procedure based on the error detection codes. The microcontroller is further configured to restore the logical-to-physical address mapping data in the volatile storage area based on a backup of the logical-to-physical address mapping data.

Abstract: A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.

Abstract: A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory. The controller is coupled to the memory for processing data transmission between the memory chip and the host. The controller further determines whether the memory chip enters a boot mode for the first time. When the memory chip enters the boot mode for the first time, the controller accesses the memory so as to obtain a correct boot image from the boot images and transmits the correct boot image to the host.

Abstract: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.

Abstract: An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged.

Abstract: A flash memory control technique with high reliability is provided. A flash memory controller provides a volatile storage area for temporary storage of logical-to-physical address mapping data between a host and a flash memory as well as error detection codes encoded from the logical-to-physical address mapping data. When reading from the volatile storage area, the microcontroller of the flash memory controller is configured to perform an error detection procedure based on the error detection codes. The microcontroller is further configured to restore the logical-to-physical address mapping data in the volatile storage area based on a backup of the logical-to-physical address mapping data.

Abstract: A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory. The controller is coupled to the memory for processing data transmission between the memory chip and the host. The controller further determines whether the memory chip enters a boot mode for the first time. When the memory chip enters the boot mode for the first time, the controller accesses the memory so as to obtain a correct boot image from the boot images and transmits the correct boot image to the host.

Abstract: An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged.

Abstract: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.

Abstract: A method for controlling read power and an open-loop read control device using the same. The open-loop read control device is used in an optical disk writer and includes a memory, a DAC and an amplifier. The optical disk writer includes a pickup head device having a laser diode. When writing is disabled, the read power of the optical disk writer for reading the disk corresponds to a specific voltage. The memory stores a relationship curve and outputs a corresponding reference value corresponding to the specific voltage. The DAC converts the corresponding reference value into an analog corresponding reference value. The amplifier receives the analog corresponding reference value and outputs a read power control voltage, which controls the laser diode to generate a substantially constant read power in the write process.

Abstract: The method for estimating recording power Pow_tilting of a tilting part of a tilting disk is shown based on a power compensation formula: Pow_comp=A*(A*K). After a focus error (FE) signal of the tilting part of the tilting disk is manipulated as a focus servo output (FOO) signal, the parameter A is derived by low-pass filtering the FOO signal. Thereafter, another parameter K is then derived from a reference lookup table by using curve fitting approach based on parameter A such that the power compensation Pow_comp could be estimated by substituting parameters A and K into the above formula. A recording power Pow_tilting of the tilting part of the tilting disk could be estimated by adding a given recording power Piwrtpwr to the power compensation Pow_comp.

Abstract: A focusing controller and the method thereof for an optical disk drive. The focusing controller includes a filter, a coupler and a focus compensator. The filter filters out a high-frequency component of the track error signal and derives an adjusted signal, while the coupler eliminates the adjustment signal from the focusing error signal so as to generate a coupled signal. The focus compensator generates a focus control signal used for controlling a position of the pick up head of the optical disk drive according to the coupled signal during a focusing operation.

Abstract: A method for controlling read power and an open-loop read control device using the same. The open-loop read control device is used in an optical disk writer and includes a memory, a DAC and an amplifier. The optical disk writer includes a pickup head device having a laser diode. When writing is disabled, the read power of the optical disk writer for reading the disk corresponds to a specific voltage. The memory stores a relationship curve and outputs a corresponding reference value corresponding to the specific voltage. The DAC converts the corresponding reference value into an analog corresponding reference value. The amplifier receives the analog corresponding reference value and outputs a read power control voltage, which controls the laser diode to generate a substantially constant read power in the write process.

Abstract: Method and device for generating a stable power control signal in a CD recorder. The power control signal for controlling a laser diode may be a read level, an erase level and a write level. A pickup device outputs a feedback control signal to a read control circuit, and a read power control voltage is thus obtained. Then, the read power control voltage is inputted to a write control circuit, which generates first and second write power control voltages. The read level equals a reference voltage added by the read power control voltage, the erase level equals the read level added by the first write power control voltage, and the write level equals the erase level added by the second write power control voltage, so the read power control voltage and thus the read, erase and write levels are automatically and dynamically adjusted as the feedback control signal varies.

Abstract: A method for determining a direct current (DC) level involved in an alternating current signal is provided. The alternating current signal is transmitted from an amplifier to an A/D (analog-to-digital) converter. When any of the extreme values of the alternating current signal is beyond the input range of the A/D converter, the alternating current signal is shifted to make both of the peak and bottom values located within the input range of the A/D converter. Then, the real extreme values are realized according to the shift level(s), the relative peak and bottom values realized after the shifting procedure, and the input range of the A/D converter. Finally, the DC level is determined according to the real peak and bottom values.