Patents by Inventor Chin-yuan Huang
Chin-yuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961738Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.Type: GrantFiled: February 12, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta Chen, Hua-Tai Lin, Han-Wei Wu, Jiann-Yuan Huang
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Publication number: 20240105619Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11939664Abstract: A semiconductor process system includes a process chamber. The process chamber includes a wafer support configured to support a wafer. The system includes a bell jar configured to be positioned over the wafer during a semiconductor process. The interior surface of the bell jar is coated with a rough coating. The rough coating can include zirconium.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Chun Hsieh, Tsung-Yu Tsai, Hsing-Yuan Huang, Chih-Chang Wu, Szu-Hua Wu, Chin-Szu Lee
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Patent number: 11923302Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.Type: GrantFiled: June 30, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
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Patent number: 11923271Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.Type: GrantFiled: July 20, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Noor E. V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
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Publication number: 20230297759Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Inventors: Feng Wei KUO, Shuo-Mao CHEN, Chin-Yuan HUANG, Kai-Yun LIN, Ho-Hsiang CHEN, Chewn-Pu JOU
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Patent number: 11675957Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.Type: GrantFiled: May 13, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei Kuo, Shuo-Mao Chen, Chin-Yuan Huang, Kai-Yun Lin, Ho-Hsiang Chen, Chewn-Pu Jou
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Publication number: 20220246509Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.Type: ApplicationFiled: April 25, 2022Publication date: August 4, 2022Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
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Patent number: 11387177Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.Type: GrantFiled: June 17, 2019Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Her Chien, Po-Hsiang Huang, Cheng-Hung Yeh, Tai-Yu Wang, Ming-Ke Tsai, Yao-Hsien Tsai, Kai-Yun Lin, Chin-Yuan Huang, Kai-Ming Liu, Fong-Yuan Chang, Chin-Chou Liu, Yi-Kan Cheng
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Publication number: 20210264094Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.Type: ApplicationFiled: May 13, 2021Publication date: August 26, 2021Inventors: Feng Wei KUO, Shuo-Mao CHEN, Chin-Yuan HUANG, Kai-Yun LIN, Ho-Hsiang CHEN, Chewn-Pu JOU
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Patent number: 11023647Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes adjusting the dummy layer location in the functional circuit when the dummy layer location is misaligned with the contact pad of the connecting substrate.Type: GrantFiled: March 14, 2018Date of Patent: June 1, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei Kuo, Shuo-Mao Chen, Chin-Yuan Huang, Kai-Yun Lin, Ho-Hsiang Chen, Chewn-Pu Jou
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Publication number: 20200395281Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
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Publication number: 20180203972Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes adjusting the dummy layer location in the functional circuit when the dummy layer location is misaligned with the contact pad of the connecting substrate.Type: ApplicationFiled: March 14, 2018Publication date: July 19, 2018Inventors: Feng Wei KUO, Shuo-Mao CHEN, Chin-Yuan HUANG, Kai-Yun LIN, Ho-Hsiang CHEN, Chewn-Pu JOU
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Patent number: 9984196Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.Type: GrantFiled: May 23, 2016Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih Ming Yang, Yi-Kan Cheng
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Patent number: 9922160Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate; and determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes performing an LVS check of the connecting substrate including the dummy layer; and adjusting the dummy layer location in the functional circuit if the dummy layer location is misaligned with the contact pad of the connecting substrate or the connecting substrate fails the LVS check. The method further includes repeating the converting step, the determining step, and the performing the LVS check step based on the adjusted dummy layer location.Type: GrantFiled: February 12, 2015Date of Patent: March 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei Kuo, Shuo-Mao Chen, Chin-Yuan Huang, Kai-Yun Lin, Ho-Hsiang Chen, Chewn-Pu Jou
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Publication number: 20170332682Abstract: The present invention provides a system and method for extracting starch from green bananas. The system includes: a pretreatment module configured to grind and homogenize the green bananas so as to form green banana slurry; an extraction module configured to receive the green banana slurry, and configured to add an extraction solvent to the green banana slurry to generate an extracted mixture of green banana starch; a separation module, wherein the extracted mixture of green banana starch is held still in the separation module, so green banana starch precipitates and green banana suspensions are precipitated and separated; a first rinsing module configured to rinse green banana starch precipitates to remove any impurities except for the starch therein, thereby forming a banana starch cream; and, a dehydration module configured to remove water from the banana starch cream to form banana starch.Type: ApplicationFiled: November 11, 2016Publication date: November 23, 2017Inventors: Chin Yuan Huang, Jyh-Yih Leu, Wen-Jen Yang, Hao-Hsun Huang
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Publication number: 20160267218Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.Type: ApplicationFiled: May 23, 2016Publication date: September 15, 2016Inventors: Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih Ming Yang, Yi-Kan Cheng
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Publication number: 20160239598Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate; and determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes performing an LVS check of the connecting substrate including the dummy layer; and adjusting the dummy layer location in the functional circuit if the dummy layer location is misaligned with the contact pad of the connecting substrate or the connecting substrate fails the LVS check. The method further includes repeating the converting step, the determining step, and the performing the LVS check step based on the adjusted dummy layer location.Type: ApplicationFiled: February 12, 2015Publication date: August 18, 2016Inventors: Feng Wei KUO, Shuo-Mao CHEN, Chin-Yuan HUANG, Kai-Yun LIN, Ho-Hsiang CHEN, Chewn-Pu JOU
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Patent number: 9361425Abstract: A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.Type: GrantFiled: April 6, 2015Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chau-Wen Wei, Cheng-Te Chang, Chin-Yuan Huang, Chih Ming Yang, Yi-Kan Cheng