Abstract: A package structure having tapering support bars and leads. The package structure has at least a lead frame, a die, a plurality of conductive wires and an encapsulating plastic body. The lead frame has a first surface and has at least a package unit. The package unit has a die pad, a plurality of leads and a plurality of support bars. The die pad is positioned in the middle. The leads and support bars are distributed around the periphery of the package unit. In addition, the width of the leads and support bars decreases gradually from a location close to the die pad towards the peripheral region. The leads and support bars have a rectangular or trapezoidal cross-section. A die is bonded on the surface of the die pad and the die is electrically connected to the leads on the lead frame via a plurality of conductive wires. Plastic material such as epoxy resin encloses the die, the conductive wires and the first surface of the lead frame.

Abstract: A multi-chip semiconductor package is proposed, in which a lead frame is formed with a chip carrier that consists of at least one supporting frame and a plurality of downwardly extending portions integrally formed with the supporting frame. As the chip carrier occupies small space, this does not impede flowing of a molding compound used for forming an encapsulant. The adjacent extending portions are provided with sufficient space therebetween for allowing the molding compound to flow through the space, so that problems of incomplete filling with the molding compound and the formation of voids can be eliminated. Moreover, the downwardly extending portions can function as a pre-stressed structure so as to closely abut a bottom of a mold cavity after mold engagement, thereby making the chip carrier well assured in position without being dislocated.

Abstract: A multi-chip semiconductor package is proposed, in which a lead frame is formed with a chip carrier that consists of at least one supporting frame and a plurality of downwardly extending portions integrally formed with the supporting frame. As the chip carrier occupies small space, this does not impede flowing of a molding compound used for forming an encapsulant. The adjacent extending portions are provided with sufficient space therebetween for allowing the molding compound to flow through the space, so that problems of incomplete filling with the molding compound and the formation of voids can be eliminated. Moreover, the downwardly extending portions can function as a pre-stressed structure so as to closely abut a bottom of a mold cavity after mold engagement, thereby making the chip carrier well assured in position without being dislocated.

Abstract: A photosensitive semiconductor package with a lid is proposed, in which a chip carrier is formed with an encapsulant thereon, and the encapsulant is formed with a cavity for exposing a semiconductor chip mounted on the chip carrier. A top of the encapsulant is structured with a groove and at least a beveled portion that descends toward the groove and is associated with the groove. When a lid is attached onto the encapsulant by using an adhesive, the groove can temporarily retain excess adhesive with its flow being directed toward the groove by the beveled portion, so that undersirable adhesive loss and adhesive flash can both be prevented from occurrence, allowing the appearance of the semiconductor package to be well maintained.

Abstract: A multi-hip semiconductor package is proposed, in which a first chip and a second chip are mounted on opposing surfaces of a lead frame in a staggered manner. This staggered arrangement assures the die bonding quality for firmly disposing the second chip in the semiconductor package without being detrimental affected by the first chip. Moreover, as both opposing surfaces of the lead frame have chips mounted thereon, a mold flow of a molding resin used in a molding process can be balanced, so that turbulence the mold flow is decreased, and void formation can be avoided. In addition, the semiconductor package can incorporate a third chip in a stacked manner with respect to the first or second chip. This therefore further improves the functionality and performance of the semiconductor package.

Abstract: A dual-die packaging technology is proposed to pack two semiconductor chips in one single package module, so that one single package module is capable of offering a doubled level of functionality or data storage capacity. The proposed dual-die packaging technology is characterized in the use of a face-to-face stacked dual-die construction to pack two integrated circuit chips, such as flash memory chips, in one single package module. The first semiconductor die has its non-circuit surface attached to the front side of the die pad of the leadframe, while the second semiconductor die has its circuit surface attached by means of adhesive layer to the circuit surface of the first semiconductor die, thus forming a face-to-face stacked dual-die construction over the die pad of the leadframe, allowing one single package module to offer a doubled level of functionality or data storage capacity.

Abstract: A quad flat non-leaded package structure for housing a sensor. The package includes a die pad, a plurality of leads, a die, a plurality of bonding wires, a packaging plastic body and a lid cover. A plurality of supporters are formed near the edges on the backside of the die pad. The plurality of leads is positioned at a well-defined distance away from the four sides of the die pad. The packaging plastic body is formed on the upper surface near the peripheral section of the leads. The space between the die pad and the leads is filled by the packaging plastic material but the bottom section of the leads and the bottom section of the supporters on the backside of the die pad are exposed. The die is attached to the upper surface of the die pad and is electrically connected to the leads using the bonding wires. The lid cover is placed over the packaging plastic body.

Abstract: A multi-chip semiconductor package is proposed, in which a first chip and a second chip are mounted on opposing surfaces of a lead frame in a staggered manner. This staggered arrangement assures the die bonding quality for firmly disposing the second chip in the semiconductor package without being detrimental affected by the first chip. Moreover, as both opposing surfaces of the lead frame have chips mounted thereon, a mold flow of a molding resin used in a molding process can be balanced, so that turbulence the mold flow is decreased, and void formation can be avoided. In addition, the semiconductor package can incorporate a third chip in a stacked manner with respect to the first or second chip. This therefore further improves the functionality and performance of the semiconductor package.

Abstract: In a dual-sided chip package without a die pad according to the invention, a first die can be fixed directly on the lead fingers of a leadframe, a support bar, or bus bars, while a second die is attached to the first die. Without a die pad, the distance between the surfaces of the dies and the plastic surface of the package therefore gets longer. Thus, the invention enables a large decrease in the probability of generating voids in the plastic and there is no need to grind the dies. Besides, it improves the vibration and floating characteristics of the dies in the manufacturing process and thus prevents the exposure of the bonding wires and the shelling off or breaking of the dies. The invention can raise the yield of chip packages.

Abstract: A leadframe with a dot array of silver-plated regions on die pad is proposed, which is designed specifically for use in the construction of an exposed-pad type of semiconductor package. The proposed leadframe is characterized by that the front side of the die pad is partitioned into a centrally-located die-mounting area and a peripherally-located ground-wire bonding area; and wherein the die-mounting area is selectively silver-plated to form a dot array of silver-plated regions, while the peripheral area of the die pad is entirely silver-plated to form a silver-plated peripheral area. In addition, the die-mounting area of the die pad can be further formed with a plurality of dimples for the purpose of increasing the contact area between the die pad and a silver-epoxy layer that is to be pasted over the die-mounting area for use to adhere a semiconductor chip to the die pad.

Abstract: A quad flat non-leaded package structure for housing a sensor. The package includes a die pad, a plurality of leads, a die, a plurality of bonding wires, a packaging plastic body and a lid cover. A plurality of supporters are formed near the edges on the backside of the die pad. The plurality of leads is positioned at a well-defined distance away from the four sides of the die pad. The packaging plastic body is formed on the upper surface near the peripheral section of the leads. The space between the die pad and the leads is filled by the packaging plastic material but the bottom section of the leads and the bottom section of the supporters on the backside of the die pad are exposed. The die is attached to the upper surface of the die pad and is electrically connected to the leads using the bonding wires. The lid cover is placed over the packaging plastic body.

Abstract: The present invention provides a package comprising a lead frame, which has a die pad and a plurality of leads located at the peripheral of the die pad. An image sensor chip has an active surface and a corresponding back surface. A plurality of bonding pads are on the active surface. A plurality of leads are electrically connected from the bonding pads to the inner leads. The image sensor chip, the die pads and the inner leads are encapsulated with a transparent molding material. A cavity is formed on a surface of the transparent molding material corresponding to the active surface. The area of the cavity, which is large enough just to cover the chip of the image sensor, has a smooth surface after a polishing process.