Patents by Inventor Chin-Yuan Ko
Chin-Yuan Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230035580Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.Type: ApplicationFiled: January 25, 2022Publication date: February 2, 2023Inventors: Yao-Jen TSAI, Chih-Fu CHANG, Sheng Chiang HUNG, Chin-Yuan KO
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Publication number: 20220406608Abstract: A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: YAO-JEN TSAI, KENG-HUI LIAO, CHIH-KAI YANG, CHIH-FU CHANG, CHIA-JEN LEU, CHIN-YUAN KO
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Patent number: 10157907Abstract: An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a second power line. The first circuit is in the DWN. The second circuit is outside the DWN and electrically connected with the first circuit. The first power line is configured to provide the first circuit with power. The second power line is configured to provide the second circuit with power. The second power line is electrically connected with the first power line. The first power line and the second power line are in different conductive layers.Type: GrantFiled: December 3, 2015Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lin Chu, Hsi-Yu Kuo, Chin-Yuan Ko
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Patent number: 9979184Abstract: An electronic device is disclosed that includes an output device and a detection circuit. The output device is coupled to an output pad, and is turned on according to a protection signal. The detection circuit is configured to detect a voltage level of a control node, to generate the protection signal based on the detected voltage level, and to switch the voltage level to a predetermined voltage level according to the detected voltage level.Type: GrantFiled: July 30, 2015Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lin Chu, Chin-Yuan Ko, Hsi-Yu Kuo
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Patent number: 9780106Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.Type: GrantFiled: December 18, 2014Date of Patent: October 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
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Publication number: 20170162558Abstract: An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a second power line. The first circuit is in the DWN. The second circuit is outside the DWN and electrically connected with the first circuit. The first power line is configured to provide the first circuit with power. The second power line is configured to provide the second circuit with power. The second power line is electrically connected with the first power line. The first power line and the second power line are in different conductive layers.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: YU-LIN CHU, HSI-YU KUO, CHIN-YUAN KO
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Publication number: 20170033557Abstract: An electronic device is disclosed that includes an output device and a detection circuit. The output device is coupled to an output pad, and is turned on according to a protection signal. The detection circuit is configured to detect a voltage level of a control node, to generate the protection signal based on the detected voltage level, and to switch the voltage level to a predetermined voltage level according to the detected voltage level.Type: ApplicationFiled: July 30, 2015Publication date: February 2, 2017Inventors: Yu-Lin CHU, Chin-Yuan KO, Hsi-Yu KUO
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Patent number: 9553508Abstract: A circuit that includes a first diode-connected dummy device, a second diode-connected dummy device, a third diode-connected dummy device, a fourth diode-connected dummy device, and a first discharge path. The second diode-connected dummy device connected in cascode with the first diode-connected dummy device. The fourth diode-connected dummy device connected in cascode with the third diode-connected dummy device. The first and the second diode-connected dummy devices are formed in a first region. The third and the fourth diode-connected dummy devices are formed in a second region which is outside the first region. The first discharge path configured to discharge charges from at least one of the first and the second diode-connected dummy devices in the first region to a reference voltage terminal of one of the third and the fourth diode-connected dummy devices in the second region.Type: GrantFiled: August 28, 2015Date of Patent: January 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lin Chu, Chin-Yuan Ko, Hsi-Yu Kuo
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Patent number: 9240401Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region.Type: GrantFiled: July 30, 2014Date of Patent: January 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Yu Kuo, Chin-Yuan Ko
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Publication number: 20150102397Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
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Patent number: 8947938Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.Type: GrantFiled: September 21, 2012Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
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Publication number: 20140339603Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region.Type: ApplicationFiled: July 30, 2014Publication date: November 20, 2014Inventors: Hsi-Yu Kuo, Chin-Yuan Ko
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Publication number: 20140085984Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.Type: ApplicationFiled: September 21, 2012Publication date: March 27, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
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Patent number: 7453280Abstract: A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.Type: GrantFiled: August 31, 2007Date of Patent: November 18, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hui Liang, Chia-Lin Chen, Pei-Chun Liao, Chin-Yuan Ko
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Publication number: 20080073724Abstract: A semiconductor device and a method for forming the same provides a double layer contact etch stop layer selectively formed over PMOS transistors with only a single silicon nitride contact etch stop layer formed over NMOS transistors on the same chip. The composite contact etch stop layer structure formed over the PMOS transistor avoids data retention and plasma induced damage issue associated with the PMOS transistor and a single silicon nitride contact etch stop layer formed over NMOS transistors avoids device shifting issues.Type: ApplicationFiled: September 22, 2006Publication date: March 27, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Hui Liang, Chia-Lin Chen, Chin-Yuan Ko
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Patent number: 7307880Abstract: An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder.Type: GrantFiled: November 14, 2005Date of Patent: December 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Yuan Ko, Yung-Sheng Tsai, Pei-Chun Liao
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Publication number: 20070109852Abstract: A non-volatile memory cell based on a soft breakdown mechanism is provided. The memory cell comprises a resistor coupled serially to a gate or source/drain regions of a MOS device. When a soft breakdown occurs to the MOS device, leakage current flowing through the gate dielectric increases. The change of the leakage current is used to indicate different states.Type: ApplicationFiled: November 14, 2005Publication date: May 17, 2007Inventors: Chin-Yuan Ko, Yung-Sheng Tsai, Pei-Chun Liao