Patents by Inventor CHIN-YUAN LO
CHIN-YUAN LO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047325Abstract: A ball grid array and a configuration method of the same are provided. The ball grid array is formed on a printed circuit board and includes an inner row region and an outer row region. The inner row region includes a plurality of first solder balls that are arranged by a first ball pitch. The first solder balls respectively correspond to a plurality of predetermined vias, and the first ball pitch is determined according to a minimum trace width that is relative to a via size of the predetermined vias. The outer row region surrounds the inner row region and includes a plurality of second solder balls that are arranged by a second ball pitch. The second ball pitch is smaller than the first ball pitch.Type: ApplicationFiled: June 15, 2023Publication date: February 8, 2024Inventors: CHIN-YUAN LO, HSIN-HUI LO
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Patent number: 11553585Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.Type: GrantFiled: December 28, 2021Date of Patent: January 10, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chin-Yuan Lo, Nan-Chin Chuang, Hsin-Hui Lo
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Publication number: 20220312579Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.Type: ApplicationFiled: December 28, 2021Publication date: September 29, 2022Inventors: CHIN-YUAN LO, NAN-CHIN CHUANG, HSIN-HUI LO
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Patent number: 11322474Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.Type: GrantFiled: March 5, 2021Date of Patent: May 3, 2022Assignee: Realtek Semiconductor Corp.Inventors: Chin-Yuan Lo, Chih-Hao Chang, Tze-Min Shen
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Patent number: 11264352Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.Type: GrantFiled: June 10, 2020Date of Patent: March 1, 2022Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Ting-Ying Wu, Chien-Hsiang Huang, Chin-Yuan Lo, Chih-Wei Chang
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Patent number: 11227854Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.Type: GrantFiled: May 12, 2020Date of Patent: January 18, 2022Assignee: Realtek Semiconductor Corp.Inventors: Chin-Yuan Lo, Nan-Chin Chuang, Chih-Hao Chang
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Publication number: 20210327844Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.Type: ApplicationFiled: March 5, 2021Publication date: October 21, 2021Inventors: Chin-Yuan Lo, Chih-Hao Chang, Tze-Min Shen
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Patent number: 10998016Abstract: A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.Type: GrantFiled: August 30, 2019Date of Patent: May 4, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chin-Yuan Lo, Ting-Ying Wu, Hsin-Hui Lo, Nan-Chin Chuang
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Publication number: 20210118846Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.Type: ApplicationFiled: May 12, 2020Publication date: April 22, 2021Inventors: Chin-Yuan Lo, Nan-Chin Chuang, Chih-Hao Chang
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Publication number: 20200402948Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.Type: ApplicationFiled: June 10, 2020Publication date: December 24, 2020Inventors: TING-YING WU, CHIEN-HSIANG HUANG, CHIN-YUAN LO, CHIH-WEI CHANG
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Publication number: 20200075066Abstract: A memory device that includes a driver IC, a voltage-dividing resistor, at least two noise-suppressing resistors and at least three memory ICs is provided. A terminal of the voltage-dividing resistor is electrically coupled to a voltage source and another other terminal of the voltage-dividing resistor is electrically coupled to the driver IC through an end a connection path. One of the memory ICs is electrically coupled to the voltage-dividing resistor and the driver IC through the end the connection path. Each of at least two of the other memory ICs is electrically coupled to the connection path through one of the noise-suppressing resistors and is further electrically coupled to the driver IC.Type: ApplicationFiled: August 30, 2019Publication date: March 5, 2020Inventors: Chin-Yuan Lo, Ting-Ying Wu, Hsin-Hui Lo, Nan-Chin Chuang
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Patent number: 9955586Abstract: A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.Type: GrantFiled: July 16, 2015Date of Patent: April 24, 2018Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Ting-Ying Wu, Cheng-Lin Wu, Chin-Yuan Lo, Wen-Shan Wang
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Publication number: 20160021745Abstract: A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.Type: ApplicationFiled: July 16, 2015Publication date: January 21, 2016Inventors: TING-YING WU, CHENG-LIN WU, CHIN-YUAN LO, WEN-SHAN WANG