Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: The present invention relates to a foldable honeycomb structure and method for making the same. The method comprises (a) providing a plurality of flat strips; (b) forming a pair of longitudinal creases in each strip thereby defining the first two longitudinal margins of each strip and a central portion of each strip between the creases; (c) folding each strip along said creases so that each folded strip has two exposed outside surfaces; (d) applying at least three longitudinal glue lines to the exposed outside surface of each folded strip; and (e) stacking the glued strips. As a result, it need not open the longitudinal margins during the process of applying the longitudinal glue lines, which can avoid the deformation of the strip and have a precise gluing position.

Abstract: The present invention relates to a foldable honeycomb structure and method for making the same. The method comprises (a) providing a plurality of flat strips; (b) forming a pair of longitudinal creases in each strip thereby defining the first two longitudinal margins of each strip and a central portion of each strip between the creases; (c) folding each strip along said creases so that each folded strip has two exposed outside surfaces; (d) applying at least three longitudinal glue lines to the exposed outside surface of each folded strip; and (e) stacking the glued strips. As a result, it need not open the longitudinal margins during the process of applying the longitudinal glue lines, which can avoid the deformation of the strip and have a precise gluing position.

Abstract: There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer.