Patents by Inventor CHIN-YUAN TSENG
CHIN-YUAN TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974479Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.Type: GrantFiled: December 11, 2020Date of Patent: April 30, 2024Assignee: INNOLUX CORPORATIONInventors: Shun-Yuan Hu, Chin-Lung Ting, Li-Wei Mao, Ming-Chun Tseng, Kung-Chen Kuo, Yi-Hua Hsu, Ker-Yih Kao
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Patent number: 11956563Abstract: A method for identifying video signal source is provided. The method includes the following steps. A first identification code is assigned to a first transmitter device by a receiver control unit of a receiver device. A first video data is transmitted by the first transmitter device. The first video data and a first identification image corresponding to the first identification code are combined as a first combined video data by the receiver control unit. The first combined video data is outputted to a display device by the receiver control unit.Type: GrantFiled: January 7, 2021Date of Patent: April 9, 2024Assignee: BenQ CorporationInventors: Chia-Nan Shih, Chen-Chi Wu, Lin-Yuan You, Chin-Fu Chiang, Ron-Kun Tseng, Chuang-Wei Wu
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Patent number: 11901190Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.Type: GrantFiled: April 30, 2018Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Yuan Tseng, Yu-Tien Shen, Wei-Liang Lin, Chih-Ming Lai, Kuo-Cheng Ching, Shi Ning Ju, Li-Te Lin, Ru-Gun Liu
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Patent number: 11848208Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first spacer over a substrate. The method includes partially removing the first spacer to form a gap dividing the first spacer into a first part and a second part. The method includes forming a filling layer covering a first top surface and a first sidewall of the first spacer. The filling layer and the first spacer together form a strip structure. The method includes forming a second spacer over a second sidewall of the strip structure. The method includes forming a third spacer over a third sidewall of the second spacer. The third spacer is narrower than the second spacer.Type: GrantFiled: August 9, 2022Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
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Publication number: 20230247817Abstract: A method (of manufacturing fins for a semiconductor device) includes: forming semiconductor fins including ones thereof having a first cap with a first etch sensitivity (first capped fins) and second ones thereof having a second cap with a second etch sensitivity (second capped fins), the first and second etch sensitivities being different; and eliminating selected ones of the first capped fins and selected ones of the second capped fins.Type: ApplicationFiled: March 27, 2023Publication date: August 3, 2023Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
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Patent number: 11616067Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.Type: GrantFiled: December 16, 2021Date of Patent: March 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
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Patent number: 11532482Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.Type: GrantFiled: February 9, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
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Publication number: 20220384190Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first spacer over a substrate. The method includes partially removing the first spacer to form a gap dividing the first spacer into a first part and a second part. The method includes forming a filling layer covering a first top surface and a first sidewall of the first spacer. The filling layer and the first spacer together form a strip structure. The method includes forming a second spacer over a second sidewall of the strip structure. The method includes forming a third spacer over a third sidewall of the second spacer. The third spacer is narrower than the second spacer.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Chih-Ming LAI, Shih-Ming CHANG, Wei-Liang LIN, Chin-Yuan TSENG, Ru-Gun LIU
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Publication number: 20220367201Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.Type: ApplicationFiled: July 25, 2022Publication date: November 17, 2022Inventors: Chin-Yuan TSENG, Yu-Tien SHEN, Wei-Liang LIN, Chih-Ming LAI, Kuo-Cheng CHING, Shi-Ning JU, Li-Te LIN, Ru-Gun LIU
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Patent number: 11437239Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming a first spacer and a second spacer respectively over opposite inner walls of the trench. The first spacer and the second spacer are spaced apart from each other. The method includes removing a first portion of the first spacer to form a first gap in the first spacer, wherein a first part and a second part of the first spacer are spaced apart by the first gap, and the first gap communicates with the trench. The method includes forming a filling layer into the trench and the first gap to cover the first spacer and the second spacer. The filling layer, the first spacer, and the second spacer together form a strip structure. The method includes removing the first layer.Type: GrantFiled: April 1, 2021Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
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Publication number: 20220108990Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.Type: ApplicationFiled: December 16, 2021Publication date: April 7, 2022Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
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Patent number: 11222899Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(?90%)*T1)?Pmin?(Gmin+(?110%)*T1).Type: GrantFiled: July 1, 2020Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
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Patent number: 11081354Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a mandrel over a substrate, the mandrel having a first sidewall and a second sidewall opposing the first sidewall; forming a first fin on the first sidewall and a second fin on the second sidewall; depositing a dielectric material covering the first fin, the second fin, and the mandrel; partially removing the dielectric material, thereby exposing the second fin; etching the second fin without etching the first fin and the mandrel; removing the dielectric material; and removing the mandrel.Type: GrantFiled: December 23, 2019Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chin-Yuan Tseng, Wei-Liang Lin, Li-Te Lin, Ru-Gun Liu, Min Cao
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Publication number: 20210225649Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming a first spacer and a second spacer respectively over opposite inner walls of the trench. The first spacer and the second spacer are spaced apart from each other. The method includes removing a first portion of the first spacer to form a first gap in the first spacer, wherein a first part and a second part of the first spacer are spaced apart by the first gap, and the first gap communicates with the trench. The method includes forming a filling layer into the trench and the first gap to cover the first spacer and the second spacer. The filling layer, the first spacer, and the second spacer together form a strip structure. The method includes removing the first layer.Type: ApplicationFiled: April 1, 2021Publication date: July 22, 2021Inventors: Chih-Ming LAI, Shih-Ming CHANG, Wei-Liang LIN, Chin-Yuan TSENG, Ru-Gun LIU
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Publication number: 20210166947Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.Type: ApplicationFiled: February 9, 2021Publication date: June 3, 2021Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
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Patent number: 10971363Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure.Type: GrantFiled: October 30, 2019Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
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Patent number: 10957551Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).Type: GrantFiled: September 16, 2019Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
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Patent number: 10950456Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.Type: GrantFiled: October 14, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
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Publication number: 20200335507Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(?90%)*T1)?Pmin?(Gmin+(?110%)*T1).Type: ApplicationFiled: July 1, 2020Publication date: October 22, 2020Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
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Patent number: 10714485Abstract: A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.Type: GrantFiled: September 10, 2018Date of Patent: July 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou