Patents by Inventor Ching-An Chung

Ching-An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12282352
    Abstract: An electronic device includes a first circuit block and a second circuit block. The first circuit block is allocated in a first power domain, and includes a first clock counter and an updating circuit. The first clock counter is arranged to generate a first counter value according to a first reference clock. The updating circuit is arranged to receive a second counter value, and update the first counter value according to the second counter value. The second circuit block is allocated in a second power domain, and includes a second clock counter arranged to generate the second counter value according to a second reference clock. The first power domain and the second power domain are controlled independently.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 22, 2025
    Assignee: Airoha Technology Corp.
    Inventors: I-Ping Huang, Ching-An Chung
  • Publication number: 20240361798
    Abstract: An electronic device includes a first circuit block and a second circuit block. The first circuit block is allocated in a first power domain, and includes a first clock counter and an updating circuit. The first clock counter is arranged to generate a first counter value according to a first reference clock. The updating circuit is arranged to receive a second counter value, and update the first counter value according to the second counter value. The second circuit block is allocated in a second power domain, and includes a second clock counter arranged to generate the second counter value according to a second reference clock. The first power domain and the second power domain are controlled independently.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Applicant: Airoha Technology Corp.
    Inventors: I-Ping Huang, Ching-An Chung
  • Patent number: 8724531
    Abstract: The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: May 13, 2014
    Assignee: Mediatek Inc.
    Inventors: Ching An Chung, Shih-Chung Yin
  • Patent number: 8140877
    Abstract: An apparatus is provided, for reducing power consumption in a system operating in a power saving mode, comprising a controller, an oscillator circuit and a voltage regulator. The controller provides a first control signal and a second control signal. The oscillator circuit, connected to the controller, wherein the controller controls the oscillator circuit according to the second control signal. The voltage regulator providing electric power to the oscillator circuit, connected to the controller, wherein the controller controls the voltage regulator according to the first control signal.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: March 20, 2012
    Assignee: Mediatek Inc.
    Inventors: Hong-Kai Hsu, Ching-An Chung
  • Publication number: 20100304780
    Abstract: The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 2, 2010
    Applicant: MEDIATEK INC.
    Inventors: Ching An Chung, Shih-Chung Yin
  • Publication number: 20090275369
    Abstract: An apparatus is provided, for reducing power consumption in a system operating in a power saving mode, comprising a controller, an oscillator circuit and a voltage regulator. The controller provides a first control signal and a second control signal. The oscillator circuit, connected to the controller, wherein the controller controls the oscillator circuit according to the second control signal. The voltage regulator providing electric power to the oscillator circuit, connected to the controller, wherein the controller controls the voltage regulator according to the first control signal.
    Type: Application
    Filed: July 16, 2009
    Publication date: November 5, 2009
    Applicant: MEDIATEK INC.
    Inventors: Hong-Kai Hsu, Ching-An Chung
  • Patent number: 7584372
    Abstract: An apparatus is provided, for reducing power consumption in a system operating in a power saving mode, comprising a controller, an oscillator circuit and a voltage regulator. The controller provides a first control signal and a second control signal. The oscillator circuit, connected to the controller, wherein the controller controls the oscillator circuit according to the second control signal. The voltage regulator providing electric power to the oscillator circuit, connected to the controller, wherein the controller controls the voltage regulator according to the first control signal.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: September 1, 2009
    Assignee: Mediatek Inc.
    Inventors: Hong-Kai Hsu, Ching-An Chung
  • Publication number: 20070249305
    Abstract: An apparatus is provided, for reducing power consumption in a system operating in a power saving mode, comprising a controller, an oscillator circuit and a voltage regulator. The controller provides a first control signal and a second control signal. The oscillator circuit, connected to the controller, wherein the controller controls the oscillator circuit according to the second control signal. The voltage regulator providing electric power to the oscillator circuit, connected to the controller, wherein the controller controls the voltage regulator according to the first control signal.
    Type: Application
    Filed: September 22, 2006
    Publication date: October 25, 2007
    Applicant: MEDIATEK INC.
    Inventors: Hong-Kai Hsu, Ching-An Chung