Abstract: A computer readable medium comprising computer executable instructions for carrying out a method is disclosed. The method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.

Abstract: The present invention provides an oral formulation for activation of autologous stem cell, comprising a stem cell activator encapsulated into a water-in-oil-in-water (W/O/W) multiple emulsion; wherein the stem cell activator induces autologous CD34+CD45+ hematopoietic stem cells (HSCs), wherein the stem cell activator is selected from the group consisting of granulocyte colony-stimulating factor (G-CSF), stem cell factor (SCF) and combination thereof. The W/O/W multiple emulsion protects the stem cell activator from stomach acid digestion, preserving its bioactivity during transport to the bone marrow (BM) via the Peyer's patches of the intestinal lymphatic system.

Abstract: A transparent antenna is provided. A transparent antenna includes a transparent dielectric substrate, a plurality of antenna conductive layers, a feeding layer and a plurality of grounding layers. The antenna conductive layers are disposed on a first surface of the transparent dielectric substrate. The feeding layer is disposed on the first surface of the transparent dielectric substrate and is connected to the antenna conductive layers. Each of the antenna conductive layer, the feeding layer and the grounding layer is a mesh structure. The antenna conductive layers and the grounding layers corresponding thereto form a plurality of antenna units. The antenna conductive layers of the antenna units are not all the same; or the grounding layers of the antenna units are not all the same.

Abstract: An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The backside semiconductor structure may have one or more different materials from the semiconductor structure. For instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. As another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure.

Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.

Abstract: Disclosed is a display device including a front light module, a first polarizing module, and a reflective display unit. A light guide plate is located between the first polarizing module and the reflective display unit. The front light module includes a light guide plate and a light source. The light source is disposed next to a light incident surface of the light guide plate. The first polarizing module includes a first polarizer and a first quarter wave plate, where the first quarter wave plate is located between the light guide plate and the first polarizer. There is a first air gap layer between the light guide plate and the first quarter wave plate. The display device disclosed has good optical efficiency and contrast.

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

Abstract: The disclosed system may include an antenna feed that has various electronic components. The system may also include a lens that has one or more layers, and an antenna embedded on at least a portion of the layers of the lens. The antenna may be electrically connected to at least one of the electronic components of the antenna feed. Various other apparatuses, wearable electronic devices, and methods of manufacturing are also disclosed.

Abstract: A two-stage system and method for treating fluoride-containing wastewater are provided. The two-stage system includes a first concentration defluoridation section and a second concentration defluoridation section. In the first concentration defluoridation section, the first mixed wastewater containing high concentration of fluoride ions is mixed with calcium chloride and stirred in the second mixing tank to obtain the second mixed wastewater containing low-concentration fluoride ions; in the second concentration defluoridation section, the second mixed wastewater is mixed with an advanced defluoridation agent and stirred in the third mixing tank to form a third mixed wastewater; the third mixed wastewater is introduced into a flocculation tank from the third mixing tank; and polymer is added for flocculation and sedimentation, so as to discharge a sediment and a defluoridation wastewater, the fluoride ion of which is less than 15 ppm.

Abstract: An advanced defluoridation agent and a method for removing fluoride ions in fluorine-containing wastewater are provided. The advanced defluoridation agent includes 40-70 wt % of polyaluminum sulfate, 0.3-30 wt % of hydroxyapatite and deionized water supplemented to 100 wt %. Using the advanced defluoridation agent of the present disclosure to treat fluoride-containing wastewater can achieve increased defluorination efficiency, reduced electrical conductivity, and reduced sludge content, and a better defluorination effect. The concentration of fluoride ions is lower than 15 ppm after using the advanced defluoridation agent of the present disclosure.

Abstract: A driving circuit includes a first driving signal generator, a first voltage conversion circuit and a first switch. The first driving signal generator generates a first driving signal according a first input signal, wherein the first driving signal is a pulse width modulated signal. The first voltage conversion circuit is coupled between the first driving signal generator and a control terminal of a first power transistor, converts the first driving signal to an output driving signal by charges a capacitor and discharges the capacitor, wherein the output driving signal is output to the control terminal of the first power transistor. The first switch is couple with the first power transistor in series, and is controlled by a control signal to be turned-on or cut-off.

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

Abstract: Multiple voltage threshold integrated circuit structures with local layout effect tuning, and methods of fabricating multiple voltage threshold integrated circuit structures with local layout effect tuning, are described. For example, an integrated circuit structure includes a first fin structure or vertical arrangement of horizontal nanowires. A second fin structure or vertical arrangement of horizontal nanowires is laterally spaced apart from the first fin structure or vertical arrangement of horizontal nanowires. An N-type gate structure is over the first fin structure or vertical arrangement of horizontal nanowires. A P-type gate structure is over the second fin structure or vertical arrangement of horizontal nanowires, the P-type gate structure in contact with the N-type gate structure with a PN boundary between the P-type gate structure and the N-type gate structure.

Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.

Abstract: Techniques and mechanisms for providing gate dielectric structures of a transistor. In an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (TMD) material. The channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. A composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. The composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. In another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.

Abstract: Techniques and mechanisms for forming a gate dielectric structure and source or drain (S/D) structures on a monolayer channel structure of a transistor. In an embodiment, the channel structure comprises a two-dimensional (2D) layer of a transition metal dichalcogenide (TMD) material. During fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to produce a conductive material. While a first portion of the dielectric material is covered by a patterned structure, a second portion of the dielectric material is exposed to a plasma treatment to form a source or dielectric (S/D) electrode structure that adjoins the first portion. In another embodiment, the dielectric material is an oxide of a Group V-VI transition metal.

Abstract: A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate. Transfer of the TMD monolayer from the growth substrate to the carrier wafer comprises mechanically lifting off the TMD monolayer from the growth substrate. The low strain transfer protective layer can limit the amount of strain transferred from the carrier wafer to the TMD monolayer during lift-off. The carrier wafer and protective layer are separated from the TMD monolayer after attachment of the TMD monolayer to the target substrate.

Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.