Abstract: A memory device including a memory array, a driver circuit, and a recover circuit is provided. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

Abstract: An electrochemical battery is fabricated with stacked layers of a lithium (Li)-sodium (Na) material. At first, on the upper and lower surfaces of a conductive substrate, a cathode, an ion transmission layer, and an anode are stacked in sequence and another conductive substrate is stacked on top of the anode. The battery is thus fabricated with bi-directionally stacking a number of the above parts. The ionic radius of Na ion is larger than that of Li ion. When Li ion is used as the conductor ion, the mobility is high as having a great energy density in favor of fast charging and discharging. When Na ion is used as the conductor ion, the Na ion has a large radius for easily obtaining a cathode featured in high capacitance. With the novel structure, the electrochemical performance of the overall battery is improved with low cost, high security, and high stability.

Abstract: A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, and a first bit line extending in a first direction, and being coupled to the first memory cell and the second memory cell. The memory circuit further includes a first source line extending in the first direction, being coupled to the first memory cell, the second memory cell and the first select transistor, and being separated from the first bit line in a second direction different from the first direction. memory circuit includes a second source line extending in the first direction, and being coupled to the first select transistor.

Abstract: The invention provides a touch display panel and a manufacturing method therefor. The touch display panel comprises a substrate; a display region disposed on the substrate; a first touch electrode disposed in the display region; a second touch electrode disposed in the display region; and a third touch electrode disposed in the display region, the first touch electrode, the second touch electrode and the third touch electrode arranged adjacently, and the third touch electrode and the second touch electrode electrically disconnected; wherein the second touch electrode is electrically connected to the first touch electrode, and an area of the third touch electrode is greater than an area of the first touch electrode and/or an area of the second touch electrode.

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

Abstract: An integrated circuit includes a sense amplifier connected to a bit line and a bit line bar, a first memory cell configured to store a data signal and selectively output the data signal on at least one of the bit line and the bit line bar in response to a word line signal, a first circuit connected between a first voltage terminal configured to receive a first external voltage and the bit line and having a first enable terminal configured to receive a first enable signal, wherein the first external voltage is different than the data signal, and a second circuit connected between a second voltage terminal configured to receive a second external voltage and the bit line bar and having a second enable terminal configured to receive a second enable signal, wherein the second external voltage is different than the data signal and the first external voltage.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

Abstract: An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the fir

Abstract: An information processing apparatus acquires a placement probability that expresses a probability of each of n items, where n is a natural number of 2 or higher, being placed at k positions, where k is a natural number of 2 or higher, converts the n items into m embedding vectors, where m is a natural number of 2 or higher, that express abstract representations of features of the n items, calculates an assignment probability that expresses a probability of assignment from the n items to the m embedding vectors, and derives, using a distribution of the placement probability and a distribution of the assignment probability, a probability expression of each of the m embedding vectors being placed at each of the k positions.

Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Abstract: One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.

Abstract: Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a set of OTP cells including a first subset of OTP cells connected between a first program control line and a first read control line. Each OTP cell of the first subset of OTP cells may include a programmable storage device and a switch connected between the first program control line and the first read control line. The first program control line may extend towards a first side of the memory array along a first direction, and the first read control line may extend towards a second side of the memory array facing away from the first side of the memory array.

Abstract: A method includes depositing a metal to form a gate layer for a first memory cell in a metallization layer of the semiconductor device. The method includes forming a plurality of semiconductor channels separated from the gate layer by a gate oxide layer. The method includes defining a plurality of gates from the gate layer. The method includes interconnecting the plurality of gates and the plurality of semiconductor channels to form a memory cell, wherein the interconnection comprises a plurality of mezzanine levels.

Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.