Abstract: An optical module carrier includes an insulation base and a lead frame, the insulation base has a vertical wall, a carrying part is extended from an inner side of the vertical wall, a functional area is formed through being surrounded by an inner side of the carrying part, a lens accommodation area is formed through being surrounded by the vertical wall and defined to be above the carrying part; the lead frame is partially embedded in the insulation base; a gel filling passage is formed on the vertical wall and located at an outer periphery of an optical lens, the gel filling passage is downwardly oriented along the vertical wall, bent and extended to the optical lens and exposed between distal ends of electric conductive pins in the insulation base. Accordingly, advantages of compact structure, small volume and low production cost are provided.

Abstract: A graft copolymer comprising a backbone polymer and a branched-chain polymer, and represented by formula (I), where A, B, Ra, Rb, Rc, Rd, Re, Rf, G1, G2, G3, G4, Y1, Y2, and k are as defined in the specification. A process for producing the grate copolymer, a process for preparing a gel polymer electrolyte including the graft copolymer, and an intermediate copolymer of the graft copolymer are also disclosed.

Abstract: A graft copolymer comprising a backbone polymer and a branched-chain polymer, and represented by formula (I), where A, B, Ra, Rb, Rc, Rd, Re, Rf, G1, G2, G3, G4, Y1, Y2, and k are as defined in the specification. A process for producing the grate copolymer, a process for preparing a gel polymer electrolyte including the graft copolymer, and an intermediate copolymer of the graft copolymer are also disclosed.

Abstract: Super capacitor including a gel electrolyte and manufacturing method thereof are provided. The gel electrolyte is one selected from a group consisting of a P(AN-EG-AN) copolymer, a P(AN-EG) copolymer, a P(EG-AN-EG) copolymer and a combination thereof.

Abstract: A supporting base for a semiconductor chip comprises a substrate, a surrounding wall and a reflection plate. The surrounding wall is formed on the substrate, and an accommodating space is formed between the surrounding wall and the substrate and is provided for receiving the semiconductor chip therein. The semiconductor chip is electrically connected to the substrate. The surrounding wall includes a cut-out portion on one side thereof. The reflection plate is extend to be bent from the substrate, and the reflection plate is configured to correspond to the cut-out portion and the semiconductor and is formed of an obtuse angle with the substrate. Therefore, with such structure, the present invention is able to achieve the effect of an increased illumination range.

Abstract: An integrated circuit assembly (10) includes a bipolar VLSI die (12) contained in a multilayer ceramic pin-grid array package (14). A bonding shelf (18) defined on a single ceramic layer contains an inner row (20) of bonding pads (26) and an outer row (22) of bonding pads (28). Bonding wires (30, 32) extend from bonding pads (34) on the die to the opposing pads on the inner and outer rows to provide an electrical interface between the die and the package. The inner and outer bonding pads are connected by metallized fingers to conductive pads (61, 65) which provide a power and signal interface with an incorporating system.The inner pads include metallized vias (24) to metallized segments on a layer other than that on which the bonding shelf is defined. Thus, the metallized fingers including the inner row of pads can extend to the pins while passing above or below, rather than between, adjacent pads of the outer row.