Patents by Inventor Ching-An Yang

Ching-An Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240412777
    Abstract: A memory device is provided, including at least one inverter, a transistor coupled between the at least one inverter and a bit line, and an assist circuit coupled to the bit line, configured to provide a negative voltage to the bit line, and configured to pull down a power supply voltage provided to the at least one inverter.
    Type: Application
    Filed: June 28, 2023
    Publication date: December 12, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Zhou YANG, Ying-Jhih SHIH, Chien-Yu HUANG, Jun-Cheng LIU, Ching-Wei WU
  • Publication number: 20240413277
    Abstract: A micro light-emitting device includes an epitaxial structure, a first electrode, a second electrode, a first contact layer and a diffusion structure. The epitaxial structure includes a first-type semiconductor layer, an active layer and a second-type semiconductor layer stacked in sequence. The second-type semiconductor layer has an outer surface relatively away from the first-type semiconductor layer. The first and second electrodes are respectively disposed on the epitaxial structure and electrically connected to the first-type and the second-type semiconductor layers. The first contact layer is disposed between the first electrode and the first-type semiconductor layer. The diffusion structure is disposed on a side of the second-type semiconductor layer away from the first-type semiconductor layer. A conductivity of the diffusion structure is less than that of the second-type semiconductor layer.
    Type: Application
    Filed: July 17, 2023
    Publication date: December 12, 2024
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: BOON KHOON TEE, You-Lin Peng, Chee-Yun Low, Wan-Jung Peng, Pai-Yang Tsai, Ching-Liang Lin, Fei-Hong Chen
  • Publication number: 20240411054
    Abstract: An optical film, comprising: a first substrate; a first plurality of prisms, disposed on the first substrate, wherein the first plurality of prisms comprises a first prism and a second prism adjacent to the first prism, wherein a first highest point of the first prism is higher than a second highest point of the second prism, wherein a top portion of an outer surface of the first prism comprises an arc shape with the arc shape comprise a highest point of the first prism.
    Type: Application
    Filed: June 7, 2024
    Publication date: December 12, 2024
    Inventors: Yi-Long Tyan, Lung-Pin Hsin, Ching-An Yang, YING-CHIH LU, RUEI-CIAN WU, Chang-Yu Chou
  • Publication number: 20240410421
    Abstract: A slide rail assembly includes a first rail, a supporting feature, a second rail and a handle. The supporting feature is arranged on one of the first rail and the second rail. The handle is movably mounted on the other one of the first rail and the second rail. When the handle is moved from a first operating position to a second operating position, the handle is configured to contact the supporting feature in order to drive the second rail to move from a predetermined position along a direction.
    Type: Application
    Filed: October 26, 2023
    Publication date: December 12, 2024
    Inventors: KEN-CHING CHEN, SHUN-HO YANG, TZU-CHENG WENG, CHUN-CHIANG WANG
  • Patent number: 12166126
    Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
  • Publication number: 20240404932
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least includes a redistribution layer, a semiconductor die, an interlink block, and a molding compound. The semiconductor die is disposed on the redistribution layer, and the interlink block is disposed on the redistribution layer and beside the semiconductor die. The interlink block includes an insulating encapsulant and through insulator vias penetrating through the insulating encapsulant. The molding compound disposed on the redistribution layer laterally wraps around the semiconductor die and the interlink block. The interlink block is spaced apart from the semiconductor die with the molding compound there-between. The through insulator vias are isolated from the molding compound by the insulating encapsulant.
    Type: Application
    Filed: May 29, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Ching-Hua Hsieh, Yi-Yang Lei
  • Publication number: 20240404953
    Abstract: Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.
    Type: Application
    Filed: July 25, 2024
    Publication date: December 5, 2024
    Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
  • Publication number: 20240394592
    Abstract: A method includes accessing a training dataset having multiple samples, where each sample includes a data point for each of multiple modalities. The method also includes generating, using a first encoder associated with a first modality of the multiple modalities, first modality embeddings for data points of the first modality in the training dataset. The method further includes, for each first modality embedding, determining a similarity metric to other first modality embeddings. The method also includes generating, using a second encoder associated with a second modality of the multiple modalities, second modality embeddings for data points of the second modality in the training dataset. In addition, the method includes training the second encoder based on a contrastive loss function to align the first modality embeddings and the second modality embeddings from different samples of the training dataset, where the contrastive loss function is weighed using the similarity metrics.
    Type: Application
    Filed: February 6, 2024
    Publication date: November 28, 2024
    Inventors: Rakshith Sharma Srinivasa, Jaejin Cho, Chouchang Yang, Yashas Malur Saidutta, Ching-Hua Lee, Yilin Shen, Hongxia Jin
  • Publication number: 20240391263
    Abstract: A printing device and the ribbon mounting mechanism thereof are disclosed. The ribbon mounting mechanism is used for mounting a first ribbon comprising a first core and a second ribbon comprising a second core having a diameter smaller than that of the first core. The ribbon mounting mechanism includes a first shaft supporting the first core of the first ribbon; a second shaft supporting the second core of the second ribbon, wherein the second shaft and the first shaft are concentrically disposed; a torque generator comprising a third shaft; a first gear set connecting the first shaft and the third shaft, and torque generated by the torque generator is transmitted to the first shaft through the first gear set; and a second gear set connecting the second shaft and the third shaft, and torque generated by the torque generator is transmitted to the second shaft through the second gear set.
    Type: Application
    Filed: May 28, 2023
    Publication date: November 28, 2024
    Inventors: FENG-YI TAI, CHING-YANG CHOU, CHE-FU HSU, CHUN-CHANG TU
  • Patent number: 12152969
    Abstract: Provided is a method for preparing a tissue section, including treating a tissue specimen with a clearing agent and at least one labeling agent to obtain a cleared and labeled tissue specimen; generating a three-dimensional (3D) image of the cleared and labeled tissue specimen; performing an image slicing procedure on the 3D image to generate a plurality of two-dimensional (2D) images; identifying a target 2D image among the plurality of 2D images to obtain a distance value of D1, which indicates the distance between the target 2D image and a predetermined surface of the 3D image; preparing a hardened tissue specimen from the cleared and labeled tissue specimen; and cutting the hardened tissue specimen near a predetermined site to obtain a tissue section, wherein the distance between the predetermined site and a surface of the hardened tissue specimen corresponding to the predetermined surface of the 3D image is D1.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 26, 2024
    Inventors: Ann-Shyn Chiang, Dah-Tsyr Chang, I-Ching Wang, Jia-Ling Yang, Shun-Chi Wu, Yen-Yin Lin, Yu-Chieh Lin
  • Publication number: 20240385463
    Abstract: An optical engine module including a display panel, a transflective layer, a polarizing reflective layer, a first bifocal lens, a first and second electrically controlled half waveplate is provided. The transflective layer is disposed between the display panel and the polarizing reflective layer. The polarizing reflective layer is configured to allow the light beam having a first polarization state to pass through, and reflect the light beam having a second polarization state. The first and second electrically controlled half waveplate are disposed between the transflective layer and the polarizing reflective layer. The first bifocal lens disposed between the first and second electrically controlled half waveplate has a first focal length for the light beam with the first polarization state, and has a second focal length for the light beam with the second polarization state.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 21, 2024
    Applicant: Coretronic Corporation
    Inventors: Tzu-Hung Lin, Chung-Yang Fang, Wen-Chun Wang, Ching-Chuan Wei, Bo-Han Cheng, Wei-Ting Wu
  • Publication number: 20240385527
    Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chun-Kai CHANG, Yu Sheng CHIANG, Yu De LIOU, Chi YANG, Ching-Juinn HUANG, Po-Chung CHENG
  • Publication number: 20240379559
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Shin-Yi Yang, Yu-Chen Chan, Ming-Han Lee, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20240379781
    Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Wei Hao Lu, Li-Li Su, Chien-I Kuo, Yee-Chia Yeo, Wei-Yang Lee, Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20240371827
    Abstract: A package structure includes a supporting base, conductive pillars, a first semiconductor die, a second semiconductor die, a first adhesive material, a second adhesive material and an isolation structure. The conductive pillars are disposed in the supporting base, and protruding out from a top surface of the supporting base. The second semiconductor die is adjacent to the first semiconductor die, wherein the first and second semiconductor dies are disposed on the supporting base and electrically connected to the conductive pillars. The first adhesive material is disposed in between the first semiconductor die and the top surface of the supporting base, and partially covering the conductive pillars. The second adhesive material is disposed in between the second semiconductor die and the top surface of the supporting base, and partially covering the conductive pillars. The isolation structure prevents a bleeding of the first and second adhesive material to an adjacent semiconductor die.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Ching-Hua Hsieh, Yi-Yang Lei, Chao-Wei Chiu, Ming-Yu Yen
  • Patent number: 12135350
    Abstract: Herein disclosed are an electronic component testing system and a time certification method. The electronic component testing system comprising a testing device and an interface device. The testing device comprises a backboard, and the backboard electrically connected to at least one test board and comprising a time certification component. The interface device, electrically connected to the testing device, provides a test instruction. Wherein the time certification component stores an authorization start time and an authorization end time. Wherein the testing device starts a test procedure according to the test instruction, the time certification component updates the authorization start time to a first stop time of the test procedure after the test procedure is completed.
    Type: Grant
    Filed: May 9, 2021
    Date of Patent: November 5, 2024
    Assignee: Chroma ATE Inc.
    Inventors: Tzu-Ching Yang, Shih-Chao Lin
  • Publication number: 20240361609
    Abstract: Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm?3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Hsin-Yu CHEN, Chun-Peng LI, Chia-Chun HUNG, Ching-Hsiang HU, Wei-Ding WU, Jui-Chun WENG, Ji-Hong CHIANG, Yen Chiang LIU, Jiun-Jie CHIOU, Li-Yang TU, Jia-Syuan LI, You-Cheng JHANG, Shin-Hua CHEN, Lavanya SANAGAVARAPU, Han-Zong PAN, Hsi-Cheng HSU
  • Publication number: 20240363350
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Patent number: 12127671
    Abstract: A slide rail assembly includes a supporting frame, a first rail, a second rail and a third rail. The first rail is movable relative to the supporting frame. The second rail is movable relative to the first rail. The third rail is movable relative to the second rail, and the second rail is movably mounted between the first rail and the third rail. The first rail can be moved to a second predetermined position from a first predetermined position in a retracting direction relative the supporting frame. The first rail can be retained at the second predetermined position so as to shorten a length of the slide rail assembly such that the third rail can be detached from the second rail easily in a limited environment.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: October 29, 2024
    Assignees: KING SLIDE WORKS CO., LTD., KING SLIDE TECHNOLOGY CO., LTD.
    Inventors: Ken-Ching Chen, Shun-Ho Yang, Wei-Chen Chang, Chun-Chiang Wang
  • Patent number: D1050918
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: November 12, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Chin-Chuan Wu, Ching-Sung Lin, Wen-Yang Yang, Chi-Feng Huang