Patents by Inventor Ching-An Yang
Ching-An Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250149973Abstract: A power supply system includes a voltage conversion circuit and at least one voltage detector. The voltage conversion circuit converts AC voltage into DC voltage. The voltage detector includes a voltage dividing circuit, a phase voltage detection circuit, and a line voltage detection circuit. The voltage dividing circuit is coupled to the voltage conversion circuit to receive AC voltage. The voltage dividing circuit includes multiple impedance elements and multiple voltage dividing nodes to output multiple divided voltages. The phase voltage detection circuit is coupled to one of the voltage dividing nodes of voltage dividing circuit to generate a phase voltage detection signal based on one of the divided voltages. The line voltage detection circuit is coupled to a part of the voltage dividing nodes of voltage dividing circuit to generate a line voltage detection signal based on a part of the divided voltages.Type: ApplicationFiled: April 27, 2024Publication date: May 8, 2025Inventors: Li-Ching YANG, Wen-Lung HUANG, Sheng-Hua LI
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Publication number: 20250137265Abstract: Disclosed is a non-interlock assembled flooring system, comprising: a base sheet layer and a surface slat layer disposed on the base sheet layer, wherein the surface slat layer includes a plurality of wood floor slats arranged side-by-side in a widthwise direction, the wood floor slats are separated by a plurality of cut grooves serving as expansion joints, and the surface slat layer has a continuous wood-grain surface formed by upper surfaces of the wood floor slats.Type: ApplicationFiled: August 22, 2024Publication date: May 1, 2025Applicant: CAROL YOUNG CORPORATIONInventors: CHANG-JEN YANG, PAO-CHING YANG, CHUN-TING YANG
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Patent number: 12275258Abstract: A printing device and the ribbon mounting mechanism thereof are disclosed. The ribbon mounting mechanism is used for mounting a first ribbon comprising a first core and a second ribbon comprising a second core having a diameter smaller than that of the first core. The ribbon mounting mechanism includes a first shaft supporting the first core of the first ribbon; a second shaft supporting the second core of the second ribbon, wherein the second shaft and the first shaft are concentrically disposed; a torque generator comprising a third shaft; a first gear set connecting the first shaft and the third shaft, and torque generated by the torque generator is transmitted to the first shaft through the first gear set; and a second gear set connecting the second shaft and the third shaft, and torque generated by the torque generator is transmitted to the second shaft through the second gear set.Type: GrantFiled: May 28, 2023Date of Patent: April 15, 2025Assignee: GODEX INTERNATIONAL CO., LTDInventors: Feng-Yi Tai, Ching-Yang Chou, Che-Fu Hsu, Chun-Chang Tu
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Patent number: 12229614Abstract: A card device and a manufacturing method thereof are disclosed. The card device includes a first substrate, a circuit board, a sensing module and a second substrate. The circuit board is disposed on the first substrate, and the circuit board includes an accommodating recess. The sensing module is disposed in the accommodating recess. The sensing module includes a sensing unit and a protective layer formed on the sensing unit, and the sensing unit is electrically connected to the circuit board. The second substrate is disposed on the circuit board. The second substrate includes an opening, and the opening exposes the protective layer.Type: GrantFiled: March 15, 2023Date of Patent: February 18, 2025Assignee: InnoLux CorporationInventors: Hui-Ching Yang, Yu-Tsung Liu, Te-Yu Lee
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Publication number: 20250054816Abstract: Methods for fabricating diode wafers and wafers to be processed process raw wafers sliced from an ingot and determines whether the raw wafers meet a fabrication specification. When the determined result is yes, the raw wafer is used as a high-grade raw wafer. When the determined result is no, the raw wafers are used as low-grade raw wafers. Next, the method calculates the ratio of the number of low-grade raw wafers with problems related to crystal oriented pits to the number of all low-grade raw wafers and determines whether the ratio is greater than a preset value. When the ratio is not greater than the preset value, the partial structure of each low-grade raw wafer is removed and the surface of each low-grade raw wafer is smoothed. Finally, diode structures are formed in the smoothed low-grade raw wafers to obtain diode wafers.Type: ApplicationFiled: August 9, 2024Publication date: February 13, 2025Inventors: SHIH-CHING YANG, TE-SUNG TU
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Patent number: 12222383Abstract: An insulation resistance detection circuit is coupled to a positive end and a negative end of a DC power source, and is used to detect a positive insulation resistance between the positive end and a ground point and detect a negative insulation resistance between the negative end and the ground point. A detection unit sets a first estimated resistance and a second estimated resistance, and acquires a first voltage based on turning on the switch and acquires a second voltage based on turning off the switch. The detection unit calculates a third voltage and a fourth voltage according to the first estimated resistance and the second estimated resistance so as to detect the positive insulation resistance and the negative insulation resistance when the third voltage is equal to the first voltage and the fourth voltage is equal to the second voltage.Type: GrantFiled: April 17, 2024Date of Patent: February 11, 2025Assignee: DELTA ELECTRONICS, INC.Inventors: Li-Ching Yang, Wen-Lung Huang, Sheng-Hua Li
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Patent number: 12191195Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.Type: GrantFiled: August 23, 2021Date of Patent: January 7, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Bo Tao, Runshun Wang, Li Wang, Ching-Yang Wen, Purakh Raj Verma, Dong Yin, Jian Xie
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Publication number: 20250001546Abstract: A polishing apparatus for double-sided polishing of semiconductor wafers including a first platen, a second platen, a wafer carrier, and a controller is disclosed. The controller is configured to perform operations including determining whether a batch of the semiconductor wafers is loaded on the wafer carrier for double-sided polishing and retrieving specification for the batch of semiconductor wafers. The operations include based on the retrieved specification, determining an amount of tuning required for one or more flatness control parameters, and based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of the semiconductor wafers. The operations include storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of the semiconductor wafers.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Inventors: Yung Hsing Chu, Yau Ching Yang, Tsung Chieh Lin, Meng Hung Li, Liang Chin Chen
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Publication number: 20240411054Abstract: An optical film, comprising: a first substrate; a first plurality of prisms, disposed on the first substrate, wherein the first plurality of prisms comprises a first prism and a second prism adjacent to the first prism, wherein a first highest point of the first prism is higher than a second highest point of the second prism, wherein a top portion of an outer surface of the first prism comprises an arc shape with the arc shape comprise a highest point of the first prism.Type: ApplicationFiled: June 7, 2024Publication date: December 12, 2024Inventors: Yi-Long Tyan, Lung-Pin Hsin, Ching-An Yang, YING-CHIH LU, RUEI-CIAN WU, Chang-Yu Chou
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Publication number: 20240391263Abstract: A printing device and the ribbon mounting mechanism thereof are disclosed. The ribbon mounting mechanism is used for mounting a first ribbon comprising a first core and a second ribbon comprising a second core having a diameter smaller than that of the first core. The ribbon mounting mechanism includes a first shaft supporting the first core of the first ribbon; a second shaft supporting the second core of the second ribbon, wherein the second shaft and the first shaft are concentrically disposed; a torque generator comprising a third shaft; a first gear set connecting the first shaft and the third shaft, and torque generated by the torque generator is transmitted to the first shaft through the first gear set; and a second gear set connecting the second shaft and the third shaft, and torque generated by the torque generator is transmitted to the second shaft through the second gear set.Type: ApplicationFiled: May 28, 2023Publication date: November 28, 2024Inventors: FENG-YI TAI, CHING-YANG CHOU, CHE-FU HSU, CHUN-CHANG TU
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Patent number: 12135350Abstract: Herein disclosed are an electronic component testing system and a time certification method. The electronic component testing system comprising a testing device and an interface device. The testing device comprises a backboard, and the backboard electrically connected to at least one test board and comprising a time certification component. The interface device, electrically connected to the testing device, provides a test instruction. Wherein the time certification component stores an authorization start time and an authorization end time. Wherein the testing device starts a test procedure according to the test instruction, the time certification component updates the authorization start time to a first stop time of the test procedure after the test procedure is completed.Type: GrantFiled: May 9, 2021Date of Patent: November 5, 2024Assignee: Chroma ATE Inc.Inventors: Tzu-Ching Yang, Shih-Chao Lin
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Patent number: 12109210Abstract: Provided is a pharmaceutical composition for treating a mast cell tumor, including a benzenesulfonamide derivative and a pharmaceutically acceptable carrier. Also provided is a method for treating a mast cell tumor in a subject in need thereof by using the pharmaceutical composition.Type: GrantFiled: September 29, 2021Date of Patent: October 8, 2024Assignee: GONGWIN BIOPHARM CO., LTDInventors: Chuan-Ching Yang, Mao-Yuan Lin, Shu-Ying Cheng, Yi-Jhen Feng
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Publication number: 20240313632Abstract: A power converter includes a power stage, a feedback circuit, a ramp generator and a controller. The power stage generates a pulse width modulation signal for forming an output voltage. The controller includes a comparator, a control logic circuit, an on-time generator and an off-time generator. The comparator generates a comparison signal according to a compensation signal from the feedback circuit and a ramp signal from the ramp generator. The control logic circuit generates a first trigger signal according to the comparison signal and an off-time pulse signal. The on-time generator generates a duty signal according to the first trigger signal. The duty signal is transmitted to the power stage for controlling a duty cycle ratio of the pulse width modulation signal. The off-time generator generates the off-time pulse signal according to the duty signal and transmits the off-time pulse signal to the control logic circuit.Type: ApplicationFiled: August 10, 2023Publication date: September 19, 2024Inventors: Ching-Jan CHEN, Chieh-Ju TSAI, Ching-Yang WU
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Patent number: 12085737Abstract: A composite optical film comprises a first optical film and a second optical film disposed on the first optical film, wherein the first optical film comprises a first substrate; a plurality of reversed prisms disposed on a bottom surface of the first substrate; and a first diffusion film disposed over a top surface of the first substrate; and the second optical film comprises a first PET film thereon having a first set of prisms and a second PET film having a second set of prisms thereon, wherein the first PET film and the second PET film are laminated together.Type: GrantFiled: March 23, 2023Date of Patent: September 10, 2024Assignee: UBRIGHT OPTRONICS CORPORATIONInventors: Yi-Long Tyan, Ching-An Yang, Yu-Mei Juan, Hsin-Yi Tsai, Yu-Cheng Hsiao, Lung-Pin Hsin, Hui-Yong Chen
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Publication number: 20240296395Abstract: A near-optimal scheduling system for considering processing-time variations and real-time data streaming includes a data parser module, a publish subscribe mechanism module, a processing time prediction module and a scheduling optimization module. In the processing time prediction module, an orthogonal greedy algorithm and a recurrent neural network are used to extract key features and then predict varying operation processing time. By formulating the scheduling problem in an integer programming form, an ordinal-optimization (OO) embedded decomposition and coordination method is established in the scheduling optimization module to provide dynamic and near-optimal schedules in a computationally efficient manner. Moreover, a publish subscribe mechanism is developed in the publish subscribe mechanism module by using subscribe and publish methods to realize real-time needs.Type: ApplicationFiled: June 1, 2023Publication date: September 5, 2024Inventors: Tsung-Han TSAI, Bing YAN, Peter B. LUH, Haw-Ching YANG, Mikhail A. BRAGIN, Fan-Tien CHENG
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Patent number: 12080622Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.Type: GrantFiled: April 18, 2023Date of Patent: September 3, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
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Patent number: 12066479Abstract: An insulation resistance detection circuit is coupled to a positive end and a negative end of a DC power source, and is used to detect a positive insulation resistance between the positive end and a ground point and detect a negative insulation resistance between the negative end and the ground point. A detection unit sets a first estimated resistance and a second estimated resistance, and acquires a first voltage based on turning on the switch and acquires a second voltage based on turning off the switch. The detection unit calculates a third voltage and a fourth voltage according to the first estimated resistance and the second estimated resistance so as to detect the positive insulation resistance and the negative insulation resistance when the third voltage is equal to the first voltage and the fourth voltage is equal to the second voltage.Type: GrantFiled: August 22, 2022Date of Patent: August 20, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Li-Ching Yang, Wen-Lung Huang, Sheng-Hua Li
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Publication number: 20240264218Abstract: An insulation resistance detection circuit is coupled to a positive end and a negative end of a DC power source, and is used to detect a positive insulation resistance between the positive end and a ground point and detect a negative insulation resistance between the negative end and the ground point. A detection unit sets a first estimated resistance and a second estimated resistance, and acquires a first voltage based on turning on the switch and acquires a second voltage based on turning off the switch. The detection unit calculates a third voltage and a fourth voltage according to the first estimated resistance and the second estimated resistance so as to detect the positive insulation resistance and the negative insulation resistance when the third voltage is equal to the first voltage and the fourth voltage is equal to the second voltage.Type: ApplicationFiled: April 17, 2024Publication date: August 8, 2024Inventors: Li-Ching YANG, Wen-Lung HUANG, Sheng-Hua LI
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Publication number: 20240238926Abstract: The present disclosure provides a sensing tool holder. The sensing tool holder includes a tool holder unit, a sensing unit and a housing. The tool holder unit includes a base and an additive body mounted on the base by an additive manufacturing method. The additive body includes an assembling structure. The assembling structure is formed on an outer surface of the additive body, and includes multiple first assembling recesses and multiple second assembling recesses for increasing the freedom of installation. The sensing unit is arranged on the assembling structure. The housing is mounted around the additive body, and covers and protects the sensing unit. A closed space is formed between the housing and the additive body.Type: ApplicationFiled: August 22, 2023Publication date: July 18, 2024Inventors: Hao-Ching YANG, Hsuan Yi LU
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Publication number: 20240234350Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.Type: ApplicationFiled: November 17, 2022Publication date: July 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Purakh Raj Verma, Ching-Yang Wen, XINGXING CHEN