Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including identifying a plurality of wordlines at an initial voltage different from a pass-through voltage, and causing an early discharge sequence to be performed with respect to the plurality of wordlines. The early discharge sequence includes ramping at least a first set of wordlines of the plurality of wordlines from the initial voltage to a ramping voltage different from the pass-through voltage.

Abstract: A slide rail kit includes a first rail, a second rail, an elastic member and an engaging member. The first rail is arranged with an engaging feature. The engaging member is movably mounted on the second rail. When the second rail is located at a retracted position relative to the first rail, the engaging member is configured to be engaged with the engaging feature of the first rail. When a force is applied to the engaging member to switch the engaging member from an engaging state to a disengaging state, the second rail is movable relative to the first rail from the retracted position along a predetermined direction.

Abstract: An offset overlap type of a modulated ferromagnetic pole piece ring and a manufacturing method thereof are provided. The modulated ferromagnetic pole piece ring comprises a plurality of ring pieces overlapped with each other. At least one ring piece comprises a plurality of main ribs, a plurality of inner ribs, and a plurality of outer ribs. The main ribs are arranged in a circular manner with intervals in between, and a plurality of first gaps and a plurality of second gaps are formed alternately between the main ribs, wherein the inner ribs are respectively located in the first gaps, and the outer ribs are respectively located in the second gaps.

Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.

Abstract: A polishing apparatus for double-sided polishing of semiconductor wafers including a first platen, a second platen, a wafer carrier, and a controller is disclosed. The controller is configured to perform operations including determining whether a batch of the semiconductor wafers is loaded on the wafer carrier for double-sided polishing and retrieving specification for the batch of semiconductor wafers. The operations include based on the retrieved specification, determining an amount of tuning required for one or more flatness control parameters, and based on the amount of tuning required for the one or more flatness control parameters, identifying, or generating a recipe to perform the double-sided polishing on the batch of the semiconductor wafers. The operations include storing statistical process control (SPC) feedback data in a database to perform one or more additional iterations of the double-sided polishing on the batch of the semiconductor wafers.

Abstract: An optical film, comprising: a first substrate; a first plurality of prisms, disposed on the first substrate, wherein the first plurality of prisms comprises a first prism and a second prism adjacent to the first prism, wherein a first highest point of the first prism is higher than a second highest point of the second prism, wherein a top portion of an outer surface of the first prism comprises an arc shape with the arc shape comprise a highest point of the first prism.

Abstract: A printing device and the ribbon mounting mechanism thereof are disclosed. The ribbon mounting mechanism is used for mounting a first ribbon comprising a first core and a second ribbon comprising a second core having a diameter smaller than that of the first core. The ribbon mounting mechanism includes a first shaft supporting the first core of the first ribbon; a second shaft supporting the second core of the second ribbon, wherein the second shaft and the first shaft are concentrically disposed; a torque generator comprising a third shaft; a first gear set connecting the first shaft and the third shaft, and torque generated by the torque generator is transmitted to the first shaft through the first gear set; and a second gear set connecting the second shaft and the third shaft, and torque generated by the torque generator is transmitted to the second shaft through the second gear set.

Abstract: Herein disclosed are an electronic component testing system and a time certification method. The electronic component testing system comprising a testing device and an interface device. The testing device comprises a backboard, and the backboard electrically connected to at least one test board and comprising a time certification component. The interface device, electrically connected to the testing device, provides a test instruction. Wherein the time certification component stores an authorization start time and an authorization end time. Wherein the testing device starts a test procedure according to the test instruction, the time certification component updates the authorization start time to a first stop time of the test procedure after the test procedure is completed.

Abstract: Provided is a pharmaceutical composition for treating a mast cell tumor, including a benzenesulfonamide derivative and a pharmaceutically acceptable carrier. Also provided is a method for treating a mast cell tumor in a subject in need thereof by using the pharmaceutical composition.

Abstract: A power converter includes a power stage, a feedback circuit, a ramp generator and a controller. The power stage generates a pulse width modulation signal for forming an output voltage. The controller includes a comparator, a control logic circuit, an on-time generator and an off-time generator. The comparator generates a comparison signal according to a compensation signal from the feedback circuit and a ramp signal from the ramp generator. The control logic circuit generates a first trigger signal according to the comparison signal and an off-time pulse signal. The on-time generator generates a duty signal according to the first trigger signal. The duty signal is transmitted to the power stage for controlling a duty cycle ratio of the pulse width modulation signal. The off-time generator generates the off-time pulse signal according to the duty signal and transmits the off-time pulse signal to the control logic circuit.

Abstract: A composite optical film comprises a first optical film and a second optical film disposed on the first optical film, wherein the first optical film comprises a first substrate; a plurality of reversed prisms disposed on a bottom surface of the first substrate; and a first diffusion film disposed over a top surface of the first substrate; and the second optical film comprises a first PET film thereon having a first set of prisms and a second PET film having a second set of prisms thereon, wherein the first PET film and the second PET film are laminated together.

Abstract: A near-optimal scheduling system for considering processing-time variations and real-time data streaming includes a data parser module, a publish subscribe mechanism module, a processing time prediction module and a scheduling optimization module. In the processing time prediction module, an orthogonal greedy algorithm and a recurrent neural network are used to extract key features and then predict varying operation processing time. By formulating the scheduling problem in an integer programming form, an ordinal-optimization (OO) embedded decomposition and coordination method is established in the scheduling optimization module to provide dynamic and near-optimal schedules in a computationally efficient manner. Moreover, a publish subscribe mechanism is developed in the publish subscribe mechanism module by using subscribe and publish methods to realize real-time needs.

Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

Abstract: An insulation resistance detection circuit is coupled to a positive end and a negative end of a DC power source, and is used to detect a positive insulation resistance between the positive end and a ground point and detect a negative insulation resistance between the negative end and the ground point. A detection unit sets a first estimated resistance and a second estimated resistance, and acquires a first voltage based on turning on the switch and acquires a second voltage based on turning off the switch. The detection unit calculates a third voltage and a fourth voltage according to the first estimated resistance and the second estimated resistance so as to detect the positive insulation resistance and the negative insulation resistance when the third voltage is equal to the first voltage and the fourth voltage is equal to the second voltage.

Abstract: An insulation resistance detection circuit is coupled to a positive end and a negative end of a DC power source, and is used to detect a positive insulation resistance between the positive end and a ground point and detect a negative insulation resistance between the negative end and the ground point. A detection unit sets a first estimated resistance and a second estimated resistance, and acquires a first voltage based on turning on the switch and acquires a second voltage based on turning off the switch. The detection unit calculates a third voltage and a fourth voltage according to the first estimated resistance and the second estimated resistance so as to detect the positive insulation resistance and the negative insulation resistance when the third voltage is equal to the first voltage and the fourth voltage is equal to the second voltage.

Abstract: The present disclosure provides a sensing tool holder. The sensing tool holder includes a tool holder unit, a sensing unit and a housing. The tool holder unit includes a base and an additive body mounted on the base by an additive manufacturing method. The additive body includes an assembling structure. The assembling structure is formed on an outer surface of the additive body, and includes multiple first assembling recesses and multiple second assembling recesses for increasing the freedom of installation. The sensing unit is arranged on the assembling structure. The housing is mounted around the additive body, and covers and protects the sensing unit. A closed space is formed between the housing and the additive body.

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

Abstract: Provided is a pharmaceutical composition for treating malignant peripheral nerve sheath (MPNST), including a benzenesulfonamide derivative and a pharmaceutically acceptable carrier. Also provided is a method for treating canine MPNST by administering the pharmaceutical composition to a subject in need thereof.

Abstract: A method for determining antenna rule for a radio-frequency (RF) device includes the steps of forming a gate structure on a substrate, forming a source/drain region adjacent to the gate structure, forming a first metal routing on the source/drain region, and then forming a second metal routing on the gate structure. Preferably, a sum of an area of the first metal routing and an area of the second metal routing divided by an area of the gate structure is less than a ratio.

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.