Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A card device and a manufacturing method thereof are disclosed. The card device includes a first substrate, a circuit board, a sensing module and a second substrate. The circuit board is disposed on the first substrate, and the circuit board includes an accommodating recess. The sensing module is disposed in the accommodating recess. The sensing module includes a sensing unit and a protective layer formed on the sensing unit, and the sensing unit is electrically connected to the circuit board. The second substrate is disposed on the circuit board. The second substrate includes an opening, and the opening exposes the protective layer.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

Abstract: A slide rail assembly includes a first rail, a second rail, a slide-facilitating device, and a retaining member. The second rail is movably mounted in a channel of, and is longitudinally displaceable with respect to, the first rail. The slide-facilitating device is movably mounted between the rails and includes an engaging feature. The retaining member is provided on the first rail and includes an elastic portion with a predetermined feature. The first rail includes a limiting feature for preventing deformation of the elastic portion. When the second rail is moved out of the channel after displacement in an opening direction with respect to the first rail, the slide-facilitating device is at a predetermined position, with the engaging feature engaged with the predetermined feature.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings.

Abstract: Method and associated system for managing and/or authenticating an energy storage device. The method includes receiving a first portion of identification information stored in a data storage attached to the energy storage device (401); analyzing the first portion of the identification information at least partially based on a device identification of the device (403); updating a second portion of the identification information stored in the data storage attached to the energy storage device based on a result of analyzing the first portion of the identification information (405).

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: An optical biometer includes a light-source module, a light-splitting module, a reference-arm, a sensing-arm and a sensing module. The light-source module emits incident-light. The light-splitting module, disposed corresponding to light-source module, divides the incident-light into reference light and sensing light. The reference-arm, disposed corresponding to light-splitting module, generates a first reflected-light according to the reference light. The sensing-arm, disposed corresponding to the light-splitting module, emits the sensing light to the eye and receives a second reflected-light from the eye. The sensing module generates a sensing result according to the first reflected-light and second reflected-light. In a first mode, the sensing light is emitted to a first position of the eye. In a second mode, the sensing light is emitted to a second position of the eye.

Abstract: Methods for fabricating diode wafers and wafers to be processed process raw wafers sliced from an ingot and determines whether the raw wafers meet a fabrication specification. When the determined result is yes, the raw wafer is used as a high-grade raw wafer. When the determined result is no, the raw wafers are used as low-grade raw wafers. Next, the method calculates the ratio of the number of low-grade raw wafers with problems related to crystal oriented pits to the number of all low-grade raw wafers and determines whether the ratio is greater than a preset value. When the ratio is not greater than the preset value, the partial structure of each low-grade raw wafer is removed and the surface of each low-grade raw wafer is smoothed. Finally, diode structures are formed in the smoothed low-grade raw wafers to obtain diode wafers.

Abstract: An insulation resistance detection circuit is coupled to a positive end and a negative end of a DC power source, and is used to detect a positive insulation resistance between the positive end and a ground point and detect a negative insulation resistance between the negative end and the ground point. A detection unit sets a first estimated resistance and a second estimated resistance, and acquires a first voltage based on turning on the switch and acquires a second voltage based on turning off the switch. The detection unit calculates a third voltage and a fourth voltage according to the first estimated resistance and the second estimated resistance so as to detect the positive insulation resistance and the negative insulation resistance when the third voltage is equal to the first voltage and the fourth voltage is equal to the second voltage.

Abstract: A slide rail assembly includes a supporting frame, a first rail, a second rail and a third rail. The first rail is movable relative to the supporting frame. The second rail is movable relative to the first rail. The third rail is movable relative to the second rail. When the slide rail assembly is at an extending state, the first rail is located at a predetermined position relative to the supporting frame, the second rail is located at an extended position relative to the first rail, the third rail is located at an opened position relative to the second rail and a rear rail section of the third rail is overlapped with a front rail section of the first rail.

Abstract: A slide rail assembly includes a first rail, a second rail, an auxiliary member, a blocking member and an operating member. The auxiliary member is arranged on the second rail. The blocking member is pivotally connected to the second rail. When the second rail is located at an extended position relative to the first rail, a blocking feature on the first rail blocks the blocking member in a first state for preventing the second rail from displacing away from the extended position along a retracting direction. When the operating member moves from a first operating position to a second operating position to drive the blocking member to move to a second state, the blocking feature does not block the blocking member in the second state, and the operating member engages with a predetermined portion of the auxiliary member to retain the operating member at the second operating position.

Abstract: A system can receive a request, and identify an attribute-based access control policy comprising a permission policy and a condition policy that is associated with performing an operation with respect to a group of computing resources with a first scope of the operation. The system can determine whether the account satisfies the permission policy for the operation, wherein determining whether the account satisfies the condition policy evaluates to true based on account attributes of the account and resource attributes of the group of computing resources in the first scope of the query operation. The system can, in response to determining that the account satisfies the condition policy, send an indication of the request as constrained by the first scope and a second scope that is based on the condition policy to a service, the service performing the operation to produce a result, and responding to the request with the result.

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Abstract: A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Abstract: An electrical connector and a cable grounding structure thereof are disclosed. A grounding structure is bridged between a connection body of the electrical connector and each cable, and includes a bridging portion, at least one clamping portion, at least one docking portion, and an elastic portion. The clamping portion is disposed on the bridging portion for clamping a covering layer of each cable, and the docking portion is extended from the bridging portion toward the connection body and electrically connected to connection body, and the elastic portion is attached and pressed against the covering layer of each cable, so as to provide good grounding contact and prevent the issue of skewing the cables and other factors that affects the soldering yield.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: Apparatuses, systems, and methods for applying a read voltage overdrive. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a pass voltage to a wordline in the array of memory cells, apply a read voltage to the wordline, and apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the wordline.