Abstract: A semiconductor structure includes a substrate, first and second channels, first and second gate structures, first source/drain structures, second source/drain structures, a separation plug, and an isolation material. The first and second channels are on the substrate. The first gate structure is across the first channel. The second gate structure is across the second channel. The first source/drain structures are on opposite sides of the first channel. The second source/drain structures are on opposite sides of the second channel. The separation plug has a first separation portion between the first and second gate structures and second and third separation portions extending laterally from the first separation portion beyond opposite sidewalls of the first gate structure in a top view. The isolation material surrounds one of the second and third separation portions in the top view.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

Abstract: A genetically engineered microorganism is provided. The genetically engineered microorganism has a higher expression level of acid-tolerant gene than a source microorganism. The acid-tolerant gene includes at least one of dsdA, dcuC and glaA. A method of preparing the genetically engineered microorganism and a method of producing a target chemical using the genetically engineered microorganism are also provided.

Abstract: A genetically modified microorganism producing black dyes is provided. The genetically modified microorganism producing black dyes includes a first exogenous nucleic acid and a second exogenous nucleic acid. The first exogenous nucleic acid includes a nucleic acid encoding an ATP-binding cassette transporter (ABC transporter), wherein the nucleic acid encoding an ATP-binding cassette transporter includes a nucleic acid for ped gene cluster. The second exogenous nucleic acid includes a nucleic acid encoding tyrosinase.

Abstract: A screwdriver includes a handle, a fixed stem, a storage assembly and an engaging mechanism. The handle includes a housing defining an inner space. The fixed stem defines an axial direction and is disposed on the housing and protrudes into the inner space. The storage assembly includes a movable stem and at least one storage seat disposed on the movable stem, and the movable stem is movably sleeved with the fixed stem. The engaging mechanism includes at least one first engaging portion disposed on the fixed stem, a second engaging portion disposed on the movable stem and a release assembly. The release assembly is operatable to abut against the second engaging portion so that the second engaging portion is disengaged from said first engaging portion, and the storage assembly is detachable from the fixed stem and removable from the handle.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

Abstract: A semiconductor device includes a first plurality of channel layers. The first plurality of channel layers extend along a first direction. The semiconductor device includes a second plurality of channel layers. The second plurality of channel layers also extend along the first direction. The semiconductor de123329-vice includes a first dielectric fin structure that also extends along the first direction. The semiconductor device includes a first gate structure that extends along a second direction. The first gate structure comprises a first portion that wraps around each of the first plurality of channel layers and a second portion that wraps around each of the second plurality of channel layers. The first dielectric fin structure separates the first and second portions from each other. The first gate structure comprises a third portion that connects the first and second portions to each other and is vertically disposed below the first dielectric fin structure.

Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

Abstract: An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.

Abstract: Systems and method for determining a topic cohesion measurement between a content item and a hyperlinked landing page are presented. In one embodiment, a plurality of content item signals is generated for the content item and a corresponding plurality of signals are generated for the hyperlinked landing page. An analysis of the corresponding signals is conducted to determine a measurement of topic cohesion, a topic cohesion score, between the content item and the hyperlinked landing page. A cohesion predictor model is trained to generate the predictive topic cohesion score between an input content item and a hyperlinked landing page. Upon a determination that the topic cohesion score is less than a predetermined threshold, remedial actions are taken regarding the hyperlink of the content item. Alternatively, positive actions may be carried out, including promoting the content item to others, associating advertisements with the content item, and the like.

Abstract: A management system capable of automatically calculating a carbon emission value of goods transportation and distribution contains an input unit, a comparison calculation unit, a computing unit, and an output unit. The input unit is configured to input expense write-off application form information and a bill of lading (B/L). The comparison calculation unit is connected to the input unit and includes a transportation carbon emission coefficient comparison module and an automatic transportation distance calculation module. The computing unit is connected with the input unit and the comparison calculation unit to perform calculations based on the B/L, thus obtaining a transportation cost and a transportation carbon emission value. The output unit is connected to the computing unit to generate an expense write-off report based on the at least one of the land transportation fees, the sea transportation fees, and the air transportation fees.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.

Abstract: The present disclosure provides a method including: generating a first private key and a public key according to a parameter set of full homomorphic encryption; encrypting test data and label by the public key to generate test data ciphertext and label ciphertext; generating a smart contract executed by a blockchain system, and transferring control of an amount of cryptocurrency from a first cryptocurrency account to the blockchain; receiving a result of a verification to a model ciphertext; when the result indicates that the model ciphertext does not pass the verification, retrieving the control of the amount of cryptocurrency; and when the result indicates that the model ciphertext passes the verification, receiving the model ciphertext and a second private key from the blockchain system, and decrypting, according to the first and second private keys, the model ciphertext to generate a model to infer the test data.

Abstract: A bicycle power-saving crank includes: a base arm connected at one end to a chainwheel and rotatable synchronously with the chainwheel; a base sprocket, fixed to the base arm and facing in the chainwheel; an outer sprocket, rotatably connected to the other end of the base arm via an outer spindle; a transmission component, rotatably connected to the base sprocket and the outer sprocket; and an outer arm, rotatably connected to the outer spindle and a pedal and rotatable synchronously with the outer sprocket. When the base arm extends horizontally in the travel direction, while the axial extension line of the outer arm forms a 12° angle relative to the horizontal extension line of the base arm. This design ensures that, throughout the pedaling process, the outer arm consistently maintains an angle of 12° relative to the base arm, regardless of its rotational angle, thereby enhancing pedaling efficiency.

Abstract: A segmentation model training method is disclosed. The segmentation model includes the following operations: inputting several first sample groups of a large sample set to a data augmentation model to generate several augmentation sample groups; generating several mix sample groups based on several second sample groups of a small sample set; inputting several mix sample groups to the data augmentation model to generate several augmentation mix sample groups; and training a segmentation model according to several augmentation sample groups and several augmentation mix sample groups, including: performing pre-training to the segmentation model according to several augmentation sample groups; and performing fine-tuning training to the segmentation model corresponding to several augmentation mix sample groups.

Abstract: An integrated circuit includes a set of active regions, a first set of contacts, a first gate, a first set of power rails, and a first set of vias. The first set of contacts overlaps the set of active regions, and a first and second cell boundary. The first gate overlaps the set of active regions, not overlapping the first and second cell boundary, and is between the first set of contacts. The first set of power rails is configured to supply a first or second supply voltage, and overlaps the first gate. The first set of vias is between the first gate and the first set of power rails, and electrically couples the first gate and the first set of power rails together. At least one active region of the set of active regions extends continuously through the first and second cell boundary.

Abstract: An integrated circuit includes a first power rail on a back-side of a wafer and being configured to supply a first voltage, a header circuit coupled to the first power rail and being configured to supply the first voltage to the first power rail, a second and third power rail on the back-side of the wafer, a fourth power rail on a front-side of the wafer, and a fifth power rail on the back-side of the wafer. The second and third power rail being configured to supply a second voltage. The fourth power rail includes a first set of conductors configured to supply a third voltage to the header circuit. The fifth power rail is configured to supply the third voltage and is separated from the first power rail in a first and second direction, and is separated from the second and third power rail in the first direction.