Abstract: An all-digital spread spectrum clock generating circuit with EMI reduction effect and a method for controlling the same utilize a digital spread-spectrum clock controlling unit to control a digital controlled oscillator, so that it can directly modulates an output clock frequency. Accordingly, the spectrum of the output clock frequency is spread, and the EMI effect due to the output clock signal is reduced. A spread-spectrum clock controller receives a reference clock counting signal and a dividing clock counting signal generated by a frequency detecting unit. After detecting and judging, the spread-spectrum clock controlling unit modulates and maintains a central frequency of the spread-spectrum clock periodically according to the two counting signals, thereby keeping a stability of the central frequency of the spread-spectrum clock signal and decreasing the complexity of the circuit design.

Abstract: An all-digital spread spectrum clock generating circuit with EMI reduction effect and a method for controlling the same utilize a digital spread-spectrum clock controlling unit to control a digital controlled oscillator, so that it can directly modulates an output clock frequency. Accordingly, the spectrum of the output clock frequency is spread, and the EMI effect due to the output clock signal is reduced. A spread-spectrum clock controller receives a reference clock counting signal and a dividing clock counting signal generated by a frequency detecting unit. After detecting and judging, the spread-spectrum clock controlling unit modulates and maintains a central frequency of the spread-spectrum clock periodically according to the two counting signals, thereby keeping a stability of the central frequency of the spread-spectrum clock signal and decreasing the complexity of the circuit design.

Abstract: The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

Abstract: The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

Abstract: A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal.

Abstract: A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal.