Patents by Inventor Ching-Chen Hao
Ching-Chen Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8609506Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: GrantFiled: November 19, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20130228826Abstract: A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jelin Wang, Ching-Chen Hao, Yi-Huang Wu, Meng Yi Sun
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Publication number: 20130207200Abstract: An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.Type: ApplicationFiled: February 10, 2012Publication date: August 15, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hung LU, Song-Bor LEE, Ching-Kun HUANG, Ching-Chen HAO
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Publication number: 20130154048Abstract: A guard ring for a through via, and a method of manufacture thereof, is provided. The guard ring comprises one or more rings around a through via, wherein the rings may be, for example, circular, rectangular, octagon, elliptical, square, or the like. The guard ring may be formed from a contact through an inter-layer dielectric layer and interconnect structures (e.g., vias and lines) extending through the inter-metal dielectric layers. The guard ring may contact a well formed in the substrate.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Lu, Song-Bor Lee, Ching-Chen Hao
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Patent number: 8314483Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: GrantFiled: November 12, 2009Date of Patent: November 20, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20120112322Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.Type: ApplicationFiled: January 16, 2012Publication date: May 10, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Patent number: 8168529Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.Type: GrantFiled: November 13, 2009Date of Patent: May 1, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20100187670Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: ApplicationFiled: November 12, 2009Publication date: July 29, 2010Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20100187671Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.Type: ApplicationFiled: November 13, 2009Publication date: July 29, 2010Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Patent number: 6995064Abstract: A thermal oxidation method for forming a gate dielectric layer for use within a field effect transistor device employs a thermal oxidizing atmosphere comprising a halogen getter material. By employing the halogen getter material, the field effect transistor device is formed with enhanced performance, in particular with respect to negative bias temperature instability lifetime.Type: GrantFiled: March 30, 2004Date of Patent: February 7, 2006Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Ching-Chen Hao, Chao-Chi Chen, Chih-Heng Shen, Chi-Hsun Hsieh
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Publication number: 20050218463Abstract: A thermal oxidation method for forming a gate dielectric layer for use within a field effect transistor device employs a thermal oxidizing atmosphere comprising a halogen getter material. By employing the halogen getter material, the field effect transistor device is formed with enhanced performance, in particular with respect to negative bias temperature instability lifetime.Type: ApplicationFiled: March 30, 2004Publication date: October 6, 2005Inventors: Ching-Chen Hao, Chao-Chi Chen, Chih-Heng Shen, Chi-Hsun Hsieh
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Patent number: 6949471Abstract: A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.Type: GrantFiled: July 31, 2003Date of Patent: September 27, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Chen Hao, Hung-Jen Lin, Min-Hwa Chi, Chih-Heng Shen
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Publication number: 20050026406Abstract: A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Inventors: Ching-Chen Hao, Hung-Jen Lin, Min-Hwa Chi, Chih-Heng Shen
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Patent number: 6756291Abstract: A method for repairing a damaged gate oxide layer while making the gate oxide layer resistant to gate oxide degradation including providing a silicon substrate having an overlying gate oxide layer and a polysilicon layer overlying the gate oxide layer; forming a polycide layer over the polysilicon layer; photolithographically patterning the polycide layer for dry etching a gate structure; dry etching a gate structure including etching through a thickness of the polycide layer including a fluorine containing etching chemistry to produce implanted fluorine in the polycide layer; and, thermally annealing the silicon substrate including the gate structure to thermally diffuse the implanted fluorine to an interface region of the gate oxide and the silicon substrate to form chemical bonds with silicon.Type: GrantFiled: January 24, 2003Date of Patent: June 29, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Ching Chen Hao, Jing Chiang Chang, Nai-Chen Lu, Chao-Chi Chen