Patents by Inventor Ching-Cheng Huang
Ching-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110291259Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.Type: ApplicationFiled: July 30, 2008Publication date: December 1, 2011Applicant: MEGICA CORPORATIONInventors: Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin
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Publication number: 20110278727Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: ApplicationFiled: July 26, 2011Publication date: November 17, 2011Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 8008776Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: February 2, 2008Date of Patent: August 30, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Publication number: 20110205720Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.Type: ApplicationFiled: February 18, 2011Publication date: August 25, 2011Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7977763Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.Type: GrantFiled: November 24, 2004Date of Patent: July 12, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Patent number: 7932603Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: October 31, 2007Date of Patent: April 26, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7919867Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: February 2, 2008Date of Patent: April 5, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7915157Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: February 2, 2008Date of Patent: March 29, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7915734Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: February 18, 2008Date of Patent: March 29, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7906849Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: February 18, 2008Date of Patent: March 15, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7906422Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.Type: GrantFiled: October 31, 2007Date of Patent: March 15, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7898058Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.Type: GrantFiled: July 14, 2008Date of Patent: March 1, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
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Patent number: 7863739Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.Type: GrantFiled: October 31, 2007Date of Patent: January 4, 2011Assignee: Megica CorporationInventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
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Patent number: 7796955Abstract: An expandable wireless transceiver is provided. The expandable wireless transceiver includes an antenna, a receiver, a transmitter and a switch connector. The antenna detects an electromagnetic signal in surrounding space and receives a signal with a first central frequency according to the detection result. The receiver receives the signal based on the detection result of the antenna. The transmitter outputs a radio-frequency signal. A third connection terminal of the switch connector provides a connective path to an expansion antenna. According to the coupling condition of the third connection terminal, the switch connector delivers the radio-frequency signal to its second connection terminal or third connection terminal. Thus, the radio-frequency signal with a second central frequency is transmitted to surrounding space through the antenna or the expansion antenna, wherein the second central frequency and the first central frequency are both in a specific band.Type: GrantFiled: July 17, 2007Date of Patent: September 14, 2010Assignee: Wistron Neweb Corp.Inventors: Jiahn-Rong Gau, Ching-Cheng Huang, Cheng-Hsiung Hsu, Tzu-Ping Lin, Chen-Chia Huang
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Patent number: 7772341Abstract: The present invention provided a norbornene compound with cross-linkable groups and their derivative polymers, wherein said cross-linkable groups were olefin or epoxy groups. Norbornene polymers with cross-linkable side chain and their block copolymers as well as modified derivatives were prepared via living ring-open metathesis polymerization method. The resulting polymers with excellent solubility and optic properties had narrow molecular weight distribution, well-controlled molecular weight, small refraction index and high transparency. They were also suitable for preparing hybrid materials with high thermal stability and chemical resistance.Type: GrantFiled: September 8, 2009Date of Patent: August 10, 2010Assignee: National Taiwan University of Science & TechnologyInventors: Der-Jang Liaw, Ching-Cheng Huang, Shou-Mau Hong, Ming-Hung Huang
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Patent number: 7728090Abstract: The present invention provided a norbornene compound with cross-linkable groups and their derivative polymers, wherein said cross-linkable groups were olefin or epoxy groups. Norbornene polymers with cross-linkable side chain and their block copolymers as well as modified derivatives were prepared via living ring-open metathesis polymerization method. The resulting polymers with excellent solubility and optic properties had narrow molecular weight distribution, well-controlled molecular weight, small refraction ration and high transparency. They were also suitable for preparing hybrid materials with high thermal stability and chemical resistance.Type: GrantFiled: September 18, 2006Date of Patent: June 1, 2010Assignee: National Taiwan University of Science & TechnologyInventors: Der-Jang Liaw, Ching-Cheng Huang, Shou-Mau Hong, Ming-Hung Huang
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Publication number: 20100087659Abstract: The present invention provided a norbornene compound with cross-linkable groups and their derivative polymers, wherein said cross-linkable groups were olefin or epoxy groups. Norbornene polymers with cross-linkable side chain and their block copolymers as well as modified derivatives were prepared via living ring-open metathesis polymerization method. The resulting polymers with excellent solubility and optic properties had narrow molecular weight distribution, well-controlled molecular weight, small refraction index and high transparency. They were also suitable for preparing hybrid materials with high thermal stability and chemical resistance.Type: ApplicationFiled: September 8, 2009Publication date: April 8, 2010Inventors: Der-Jang Liaw, Ching-Cheng Huang, Shou-Mau Hong, Ming-Hung Huang
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Publication number: 20100038803Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: October 31, 2007Publication date: February 18, 2010Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Patent number: 7645915Abstract: A composite dressing including a first polymeric layer, a second polymeric layer, a metal oxide, and a pharmaceutical active material is provided. The second polymeric layer is biocompatible and is disposed on a surface of the first polymeric layer. The metal oxide is distributed inside or on at least one surface of the first polymeric layer, while the pharmaceutical active material is distributed inside or on at least one surface of the second polymeric layer.Type: GrantFiled: December 11, 2007Date of Patent: January 12, 2010Assignees: Medical and Pharmaceutical Industry Technology and Development Center, National Applied Research LaboratoriesInventors: Ching-Cheng Huang, Su-Huei Lai, Yung-Sheng Lin, Ting-Kai Leung
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Publication number: 20090289346Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.Type: ApplicationFiled: July 30, 2009Publication date: November 26, 2009Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Ching-Cheng Huang, Mou-Shiung Lin